Design Technology Committee - PowerPoint Presentation

1. Design Technology CommitteeDTC Update at CEDA BOG MeetingThomas HarmsChairman DTC6-Nov-2011

2. DTC Status UpdateOver the past 12 months the DTC worked with EDA vendors in 2 study groups to discuss technical requirements in functional verification and digital implementation design flowsFocus on timeline for next 12 – 18 monthsActivity brought the DTC member companies closer together by establishing a common set of requirementsNeed to leverage this momentum for next topics/ activititesResponsiveness from EDA vendors was lackingLittle good interactions in technical team discussionsNot much feedback on requirementsNo information on timelines/ roadmaps for implementationDesign Technology Committee

3. Constraints and Scope of DTCDTC comprised of CAD managers with lots of involvement with EDA vendorsHigh sensitivity of the confidential nature of contract related aspects as well the general topic of collusionThis limits our ability to address certain topicsTechnical focus regarding joint EDA requirements worked wellNew focus likely in longer term EDA roadmaps (3+ years out) and standardsCooperation potential with DATC, CANDE on contributions to ITRSDesign Technology Committee

4. Design Technology CommitteeDTC Gap Analysis Study GroupsEffort Completion ReportDesign Technology Committee (DTC)Digital Implementation, Functional VerificationDAC, June 4, 2012

5. Outline of PresentationPresent to industry and academia the DTC assessment of EDA tools gap severity and projected progress towards gap resolutionHelp EDA industry to see disconnects viewed collectively by all DTC membersHelp academia to see areas where EDA industry is not doing enough to address design needsLessons learnedConclusions and discussions on how to move forward from hereDesign Technology Committee

6. Motivation for Current Study Groups(from DAC 2011 presentation)Establish a common set of gaps and requirements of current EDA capabilities based on the needs of the DTC member companiesAlign with EDA vendors to enable efficient use of precious EDA R&D resourcesEngage in more dialogues on methodologies, flows, advances in tool technologies and use modelsDrive EDA roadmaps

7. Status of ActivitiesOver the past 12 months DTC member company representatives have held many telephone conferences with individual EDA company representatives on our combined EDA requirements for the next 12 – 18 monthsExplanations and discussions around the DTC’s EDA requirements in digital implementation and functional verification Expectations of feedback by the EDA vendors regarding the implementation timeline of these requirementsDesign Technology Committee

8. Digital Implementation High Level GapsGap DescriptionGap Severity – DTC viewGap Severity – EDA viewProgress Towards Gap ResolutionPower and Power Grid / IR Analysis: Accuracy & Silicon Correlation (including Early Analysis) Vector-less Techniques Performance & Capacity (incl. derivation of Switching Activities)Clock Tree Synthesis / Insertion: Process Variation Aware Clock Tree Synthesis Better support of Hybrid Distributions (trees & grids combined) Better Pre-route and Metal Fill EstimationPhysical Synthesis – see the next slidePower Optimization: Needed at each step in the Flow (incl. Early Power Optimization) Multi-Vt Optimization, Cell Sizing & Buffering for timing & powerRoute: Quality of Results (incl. DFM, timing & SI closure, fill awareness) ThroughputECO: Logic Based ECO Timing Closure Driven ECO Circuit Based ECO (incl. late changes in macro, I/O block, IP)Design Technology CommitteeTable highlighting 3 attributes of individual gaps:Gap severity as perceived by DTCView of the gap severity by EDA vendors as perceived by DTCProjected progress towards gap resolution as perceived by DTCThe gap severity and slowness of the progress towards resolution highlighted by a bar length and color coding

9. Physical Synthesis Detailed GapsGap DescriptionGap Severity – DTC viewGap Severity – EDA viewProgress Towards Gap ResolutionQuality of Results: Routing Layer and Routing Rule Aware Buffering Over-buffering Avoidance Placement Improvements to Increase Cell Utilization % Support for Regular StructuresTiming Convergence: Less Miscorrelation due to Virtual Route Better correlation between Synthesis, P&R, Timing Sign-offWiring Friendly Implementation: Need to Plan Early in the Flow Include Estimated Metal Fill EffectsCapacity, Runtime and Overall Design Closure: Improved Tool Runtime Improved Time for Overall Timing/Design Closure Incremental Synthesis for Late Design Changes Improved CapacityMulti-VDD Capabilities: Flow Maturity to handle Multi-voltage DomainsAdvanced OCVDesign Technology Committee

10. Gap DescriptionGap Severity – DTC viewGap Severity – EDA viewProgress Towards Gap ResolutionPerformance, Capacity, Cost: Faster runtimes of tools and algorithms Support of multi-core architectures, better multi-threading Cost of emulation must be containedMethodology: Verification plans for digital, analog, pre- and post-silicon Full support of mixed methodological approaches Efficient debugging for software and hardware Integrated test and debug flows from pre-silicon to post-siliconUsability: Formal Verification (e.g., counterexample traces, assertions) Emulation (e.g., debugging, connection to simulation, reusability) Verification IP (e.g., Self contained, reusable, quality, ownership)Standardization: Full compliance and same interpretation of available standards Integration of coverage into verification management UVM compliant and standardized simulation environment Industry standardized Verification IP quality metricsFunctional Verification High Level GapsDesign Technology Committee

11. Lessons LearnedTechnical discussions actually took place with the different vendorsInteractions varied from curious, interested and interactive to reserved, careful questions and unidirectional information flowThere was very little sharing of responses to the DTC requirements and even less on implementation timelinesWhile there had been interest also by the EDA vendors to engage in this activity it eventually lacked follow-throughSharing of information about near-term implementation timelines apparently hampered by accountants and lack of a common NDADesign Technology Committee

12. Conclusions, Discussion on Next StepsWhile we urgently need the outlined near-term requirements, the focus on the next 12 – 18 months appears ill-suitedHow can we leverage the experiences from this activity and turn this into a highly interactive and bidirectional exchange of requirements and information moving forward?Would a common NDA overcome the barrier for bidirectional information exchange?Should we continue to focus on 12 – 18 months out?Or look to a 2 – 5 year horizon instead?…. Design Technology Committee