Andrew B Kahng Seokhyeong Kang VLSI CAD LABORATORY UC San Diego 49 th Design Automation Conference June 6 th 2012 Outline Background and Motivation Accuracy Configurable Adder Design ID: 612360
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Slide1
Accuracy-Configurable Adder for Approximate Arithmetic Designs
Andrew B. Kahng,
Seokhyeong Kang
VLSI CAD LABORATORY,
UC
San Diego
49
th
Design Automation Conference
June 6
th
, 2012Slide2
Outline
Background and Motivation
Accuracy Configurable Adder Design
Experimental Setup and Results
Conclusions and Ongoing WorksSlide3
Why Approximate Designs?
Threats to traditional IC design approach ...
Extreme variations:
PVT variation uncertainty lead to design overhead
Reliability issues:
Hard errors (NBTI, latchup), Soft errors (α-particle)Cost: Cost (power/performance) of perfect accuracy is too high!Approximate designsRelaxing the requirement of correctness can dramatically reduce costs of the design
What is the square root of 10 ?
“a little more
than three”
“3.162278....”
Approximation could be faster and more powerful
Threats to traditional IC design approach ...
Extreme variations
/
Reliability issues
/
Cost:
Approximate designs
Relaxing the requirement of correctness can dramatically reduce costs of the designSlide4
Previous Approximate Adders
Lu et al. IEEE Computer 2004
Zhu et al. TVLSI 2010
Output accuracy is fixed
b
enefits
can be
limited by required accuracy
Faster adder w/ shorter carry chain
High performance with small error rate
Large area overhead: not applicable for low energy designETAI : accurate part + inaccurate partReduce error sizeError rate is high Slide5
Our Work: Accuracy-Configurable Approximate Adder
Accuracy-configurable design adapts to changing requirements by using different modes in each situation
How power benefits
can be achieved …Slide6
Our Work: Accuracy-Configurable Approximate Adder
How power benefits
can be achieved …
Accuracy-configurable approximate adder
Mode 1: turn-off
ECC-1, ECC-2
accuracy: 90%
accuracy: 95%
Mode 2: turn-off
ECC-2Mode 3: turn-on All ECCaccuracy: 100%
approximate
addererror collection(ECC-1)
error collection(ECC-2)Slide7
Outline
Background Motivation
Accuracy Configurable Adder Design
Experimental Setup and Results
Conclusions and Ongoing WorksSlide8
Approximate Adder Implementation
16-bit adder case
Carry chain is cut to reduce critical path delay
Sub-adders generate results of partial summation
Middle sub-adder improves
accuracy (error 50%
5.5%)Slide9
Approximate Adder Implementation
N-bit adder case
Probability of correct result :
Approximate adder can
be configured with “k”
Estimation over CLA (N=16)
K
2
3
4
5
6
Min. clock cycle0.50.650.750.830.89area
0.871.051.121.151.12power0.440.680.840.951.00pass rate
0.554
0.829
0.942
0.982
0.995
carrySlide10
Error Detection and Correction
Error can be detected and corrected with small overhead
Error detection: ‘and’ gates
Error correction:
incrementor
circuit
Error detection and correction can take more time than critical path delay of “sub-adder”; the throughput can be reduced
Variable latency
operationSlide11
Accuracy Configuration with Pipeline
Config
.
Power-
gating
Accuracy
Power
reductionMode-1None
1.000-11.5%Mode-2
Stage 40.96012.4%Mode-3Stage-3, 40.92531.0%Mode-4Stage-2, 3, 40.900
51.6%
Each stage generates a result with different accuracyCan turn off later stages with power gating according to accuracy requirement
power gating
power gating
power gatingSlide12
Outline
Background Motivation
Accuracy Configurable Adder Design
Experimental Setup and Results
Conclusions and Ongoing WorksSlide13
Experimental Setup and Metrics
Metric
Definition
Data type
ACC
amp
1-|
Rc-Re|/R
cAmplitude dataACCinf
1-Be/BwInformation data
Experimental Setup
Library: TSMC 65GPImplementation: Synopsys Design CompilerSimulation: Cadence NC-SIMInput patterns: random data and actual dataLibrary preparation: Cadence Library Characterizer
Accuracy Metrics Rc and Re : correct and obtained resultsBe: number of error bits, Bw
: bit-width of dataSlide14
Approximate Adder Comparison
Accuracy vs. power consumption
Image smoothing
(Gaussian filter)
Original image
Accurate adderACA (PSNR 24.5dB)ETAI (25.3dB)
ETAII (16.2dB)
LU (11.1dB)(c)~(f) have 50% power of accurate adder (b)
(a)
(b)
(c)
(d)(e)(f)* ETAI cannot detect and correct errorsSlide15
Approximate Adder Comparison
Accuracy vs. power consumption w/voltage scaling
Voltage
scaling
(1.0V~0.6V)
ACA adder shows fine results
(accuracy vs. power)
on both
ACC
amp
and ACCinf
metricsSlide16
Accuracy Configuration and Power Saving
Power saving from voltage scaling + mode change
4-stage 32-bit adder case
accurate
result
mode change
voltage scaling
Accuracy
configuration w/
m
ode change is more
effective than w/ voltage scaling
voltage scaling
mode change
4X
reduction
Accuracy:
1.0 → 0.9Slide17
Accuracy Configuration and Power Saving
Power consumption when accuracy requirement is varying
(w/ SPEC 2006 benchmarks)
Average 30% power savings
over no accuracy configuration
High accuracySlide18
Outline
Background Motivation
Accuracy Configurable Adder Design
Experimental Setup and Results
Conclusions and Ongoing WorksSlide19
Conclusions and Ongoing Works
RTL
Required accuracy
exact
adder
approximate
adder
Synthesis
Accuracy estimation
Conclusions
We proposed accuracy-configurable approximate (ACA) adder, which can adapt to changing accuracy requirement
ACA can provide 30% power reduction with accuracy configuration during runtime
Ongoing Works
Accuracy-configurable design for other arithmetic units (multiplier, divider)
Automated synthesis flow (minimize power under the required accuracy)Slide20
Thank
You!Slide21
Accuracy-Configurable Approximate Design
Required accuracy can change during runtime
Idea of High-Efficiency Math
highlighted by Intel Labs at ISSCC-2012
Variable-precision floating point unit w/ accuracy tracking : 24-bit
12-bit 6-bit as needed
Variable-precision Mantissa
Accuracy-configurable design adapts to changing requirements, maximizing benefits of approximate design paradigm