PrimeTime Speaker Bob Tsai Advisor Jie Hong Roland Jiang Introduction Flow On Chip Variation OCV Manualautomated netlist editing Signal integrity and crosstalk Outline PrimeTime ID: 372890
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Slide1
Timing sign-off with PrimeTime
Speaker: Bob TsaiAdvisor: Jie-Hong Roland Jiang Slide2
IntroductionFlowOn Chip Variation (OCV)Manual/automated
netlist editingSignal integrity and crosstalkOutlineSlide3
PrimeTime VX, PrimeTime SI
Sign-offA collective name to a series of verification stepsStandard Parasitic Exchange Format
Represent parasitic data of wires in a chip in ASCII format
Used for delay calculation and ensuring the signal integrity
IntroductionSlide4
Flow
Setup Design
Create CHIP constraints
CHIP level STA
P&R
Tape-out
Timing error?
Timing error?
Update
SDC
Update
RTL
pass
fail
Check setup
Validate
Prelayout
Constraints
V
alidate Constraints Hand-off
Validate
Postlayout
Constraints
Update
SDC
fail
passSlide5
Models the small difference in operating parameters across the chip
Setup check: max delay for data path and min delay for clock pathHold check:
min
delay for data path and
max
delay for clock path
On Chip VariationSlide6
Setup Time Checking
D Q
D Q
logic
CT3
CT2
CT1
CLK
0.48/0.6
0.64/0.8
0.52/0.65
max =
3.04/3.8
min =
1.6/2.0
Clock path 1 = 0.8+0.6 =1.4
Data path max = 3.8
Clock path 2 = 0.64+0.52=1.16
Setup = 0.2
=> The clock period must be at least 1.4+3.8-1.16+0.2=4.24
Clock path 1 + data path max – clock path 2 + setup
clock period
setup = 0.2Slide7
Hold Time Checking
Clock path 1 = 0.64+0.48 =1.12Data path min = 1.6Clock path 2 = 0.8+0.65=1.45Hold = 0.1
=> No hold violation exists because 1.12+1.6-1.45-0.1=1.17
0
Clock path 1 + data path min – clock path 2 - hold
0
D Q
D Q
logic
CT3
CT2
CT1
CLK
0.48/0.6
0.64/0.8
0.52/0.65
max =
3.04/3.8
min =
1.6/2.0
hold = 0.1Slide8
Functions for check and analysis
Commands
Main
functions
set_wire_load_model
(before
P&R
)
read_sdf
(after P&R)
read_parasitics(after P&R)
check_timingChecks for constraint problem such as undefined clocking, input data arrival times, and output data required times. (must-do)
report_designLists the attributes of the design, including the chosen operating conditions, wire load information, and design rules.report_clock
Generates a report on the clocks defined for the design, showing for each clock the name, period, rise and fall times, and timing characteristics such as latency and uncertainty.Slide9
size_cellinsert_buffer
| remove_bufferswap_cell
Use
write_change
to output the changes
Manual
Netlist
EditingSlide10
The design should be fully placed and routed, including clock trees, but without corefiller
fix_eco_timing –type {setup | hold}fix_drc_timing –type {max_transition | max_capacitance
|
max_fanout
} –method {
size_cell | insert_buffer
}
Automated
Netlist
Editing
pt_shell>
fix_drc_timing –type max_transition –method {size_cell} -verbose
pt_shell> fix_drc_timing
–type max_transition –method {insert_buffer} -
buffer_list {BUFX1 BUFX2 BUFX3} -verboseSlide11
Signal integrityThe ability of an electrical signal to carry information reliably and resist the effects of high-frequency electromagnetic interference from nearby signals
CrosstalkThe undesirable electrical interaction between two or more physically adjacent net due to capacitive cross-couplingSignal Integrity and CrosstalkSlide12
Noise analysis flow
Enable crosstalk analysis
s
et
si_enable_analysis
TRUE
Read coupled parasitic data
read_parasitics
-format
spef -
keep_capacitive_coupling [spef_filename]
Do coupled delay analysis update_timing
Noise analysis
update_noise
Generate noise report
report_noise
Slide13
Thanks for your attentionSlide14
Clock Setup
set_false_pathset_false_path
–from CLK1 –to CLK2
set_false_path
–from
CLK2 –to CLK1
set_false_path
–from
CLK3
–to
CLK4set_false_path –from CLK4 –to CLK3set_false_path –from CLK1 –to
CLK4set_false_path –from CLK4 –to CLK1set_false_path –from CLK2
–to CLK3set_false_path –from CLK3 –to CLK2
set_clock_groupset_clock_groups \-
logically_exclusive –name E1 \-group {CLK1 CLK3}-group {CLK2 CLK4}set_active_clock [all_clocks]
D Q
CLK1
CLK2
SEL
0
1
CLK3
CLK4
0
1
D Q
logic