1 5 ACLK 32768kHz Timer count ex TA0R Interrupt Note Timer Settings Upmode CCR07 CCR1 7 CCR21 Interrupts Enabled CCR1CCR2overflow CCR1 Interrupt overflow ID: 586074
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Slide1
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
Note:
Timer Settings :
Upmode
/ CCR0=7 / CCR1 =7/ CCR2=1
Interrupts
Enabled: CCR1/CCR2/overflow
CCR1
Interrupt
overflow
Interrupt
CCR2
Interrupt
B
A
C
Normal operationSlide2
Case A: Timer is cleared in A duration
ex
: TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
overflow
Interrupt
CCR2
Interrupt
Timer
Clear
In my understanding, this interrupt will happen.
Is my understanding correct?
Timer
RestartSlide3
Case B: Timer is cleared in B duration
ex: TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
overflow
Interrupt
CCR2
Interrupt
Timer
Clear
In my understanding, this interrupt will happen.
Is my understanding correct?
Will the value of TA0R not count up at thi
s rising edge?
Is the value of TA0R clear when the TACLR was enabled
Timer
RestartSlide4
Case C: Timer is cleared in C duration
ex: TA0CTL |= (MC_1 | TACLR);
6
7
1
2
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
overflow
Interrupt
CCR2
Interrupt
Timer
Clear
0
Is this interrupt occurred?
Will the value of TA0R count up at thi
s rising edge?
Timer
Restart