Mark Grover Prof Greg Steffan Dept of Electrical and Computer Engineering Hard and Soft Processors Hard Processors Soft Processors Verilog Made from transistors Cost millions to make ID: 534896
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Slide1
Specific Choice of Soft Processor Features
Mark
Grover
Prof. Greg Steffan
Dept. of Electrical and Computer EngineeringSlide2
Hard and Soft Processors
Hard
Processors
Soft
Processors
Verilog
Made from transistors
Cost millions to make
Faster in speed
Consume
less power
Built on FPGA Fabric
Are customizable
Can cater to application specific needs
Processor ArchitectureSlide3
Research Problem
Choose the best micro-architectural features
Want to optimize the use of resources
Power consumption(as minimum as possible)Area(as less as possible)
Wall Clock Time(lesser the better)Time SpentSlide4
SPREE
Soft Processor Rapid Exploration Environment
Scanned the whole of design space
Is it viable enough?What if a new application comes into picture?
What if the performance criteria changes?Say, the user doesn’t care about area any more?Slide5
Enhanced Simulator
(MINT)
Research Objective
Enhanced Simulator
Part 1
Maximum power, area
Software Application
Fastest micro-architectural combination
What if a new application comes into picture?
What if the performance criteria changes?
Enhanced Simulator
Part 2
ApproximatesSlide6
Outline
Motivation
Implementation
Implementation Scheme(in general)Data deciphering
ResultsMultiplier optionDiscussionConclusionLong Term GoalSlide7
Implementation Scheme
Experimental Data for some Benchmarks
Look for trends and dependencies
Propose a suitable relationship
Comparing with the trade-offs and providing the best solutionSlide8
Data Deciphering
Multiplier option(Hard/Soft Multiplier)
Approximate cycle count change on using them?
Multiplication operation is converted to a set of shifts and addsSimulated the algorithm to find the equivalent number of instructions
Plotted the number of equivalent instructions vs. the changes in cycle counts(experimental data)Slide9
Hard and Soft Multiplier
Hard Multiplier
Does the multiply operation as a single instruction
Occupies finite area
Delays the clock by a finite timeConsumes finite amount of power
Soft MultiplierNo dedicated multiplierEach multiply instruction converted into simpler instructions
No change in area, frequency or powerSlide10
Method of Analysis
A*B
Set of Branches, Shifts and Add instructions
For all multiply instructions in the benchmark
Plot with the change in cycle count
(experimental)for
all
processor variants
Total change in equivalent instructionsSlide11
Outline
Motivation
Implementation
Implementation Scheme(in general)Data deciphering
ResultsMultiplier optionDiscussionConclusionLong Term GoalSlide12
Results
Gnuplot
used to plot graphs on log scale
A linear correlation obtained between the points plottedSlide13
Example 1
Increase in cycle counts(Log Scale)
Change in equivalent instructions from hard-multiplier to soft multiplier on pipe5,barrelshift procSlide14
Example 2
Increase in cycle counts(Log Scale)
Change in
equi
. instructions from hard-multiplier to soft multiplier on serial shift, high rise processorSlide15
Outline
Motivation
Implementation
Implementation Scheme(in general)Data decipheringResults
Multiplier optionDiscussionConclusionLong Term GoalSlide16
Discussion
“Fit.log” as a good measure of correlation
Percentage uncertainty is expressed by Asymptotic Standard Error(A.S.E)
Example 1- A.S.E is 4.132%Example 2- A.S.E is 3.166%A linear dependence is found on log scale
Generated by
gnuplotSlide17
A.S.E of all Processor VariantsSlide18
Outline
Motivation
Implementation
Implementation Scheme(in general)Data decipheringResults
Multiplier optionDiscussionConclusionLong Term GoalSlide19
Conclusion
Linear fit enables to predict quite accurately the change in cycle count with change in feature
This change for all the features servers as input to part 2 of the enhanced simulator
Template for future workSlide20
Example 2
Increase in cycle counts(Log Scale)
Change in
equi
. instructions from hard-multiplier to soft multiplier on serial shift, high rise processor
From part 1 of MINT by running the application on it
This gives the approx. change in cycle count for new applicationSlide21
Future Work
Presently, dealt only with the multiplier option
Similar analysis on other features
Comparison between user demands and approximate cycle countsSlide22
References
Improving Pipelined Soft Processors with Multithreading
, Martin
Labrecque and J. Gregory SteffanApplication-Specific Customization of Soft Processor
Microarchitecture, Peter Yiannacouras, J. Gregory Steffan and Jonathan RoseSlide23
Special Thanks
Prof. Greg Steffan
CARG(Compiler & Architecture Reading-Group)
PaCRaT(Parallelism and Customization Research At university of Toronto)Slide24
What I learnt?
Research is not a 9 to 5 Job, it’s a lifestyle of discovering something small but relevant from time to time
At times, you see that nothing is bearing fruits for you, then is the time to get off from your seatSlide25
Thanks
Any Questions ???