It can be used to check for design errors eg the product of two negative numbers should always result in a positive number and also to check for input or signal errors eg two signals should never be 1 at the same time For example say that the signal ID: 36689 Download Pdf

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It can be used to check for design errors eg the product of two negative numbers should always result in a positive number and also to check for input or signal errors eg two signals should never be 1 at the same time For example say that the signal

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VHDL EXAMPLE ASSERTION STATEMENT - Spring 2003 Assertion statements, along with Report statements, are often used to check for the correctness of operation of your system. It can be used to check for design errors (e.g., the product of two negative numbers should always result in a positive number), and also to check for input or signal errors (e.g., two signals should never be ’1’ at the same time). For example, say that the signal a.value should always be less than or equal to max.value. The following statement makes this ”assertion”. If the assertion is NOT true then the

VHDL simulator will report the assertion violation. assert a.value = max.value report ”a.value too large”; Say that the two signals a.sig and b.sig should never be ’1’ at the same time. The assertion statement can be used to test for this as follows: assert a.sig=’1 nand b.sig=’1 report ”a.sig and b.sig equal 1 at the same time”;

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