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VHDL EXAMPLE ASSERTION STATEMENT  Spring  Assertion statements along with Report statements VHDL EXAMPLE ASSERTION STATEMENT  Spring  Assertion statements along with Report statements

VHDL EXAMPLE ASSERTION STATEMENT Spring Assertion statements along with Report statements - PDF document

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Uploaded On 2015-02-19

VHDL EXAMPLE ASSERTION STATEMENT Spring Assertion statements along with Report statements - PPT Presentation

It can be used to check for design errors eg the product of two negative numbers should always result in a positive number and also to check for input or signal errors eg two signals should never be 1 at the same time For example say that the signal ID: 36689

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