– 1 – Data Converters Algorithmic ADC Professor Y. Chiu - PowerPoint Presentation

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– 1 – Data Converters Algorithmic ADC Professor Y. Chiu - PPT Presentation

EECT 7327 Fall 2014 Algorithmic Cyclic ADC Algorithmic Cyclic ADC 2 Data Converters Algorithmic ADC Professor Y Chiu EECT 7327 Fall 2014 Input is sampled first then circulates in the loop for N clock cycles ID: 682789

adc algorithmic converters data algorithmic adc data converters professor 7327 fall 2014 chiu eect gain bit issue error jssc

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Slide1

– 1 –

Data Converters Algorithmic ADC Professor Y. ChiuEECT 7327 Fall 2014

Algorithmic

(Cyclic) ADCSlide2

Algorithmic (Cyclic) ADC–

2 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Input is sampled first, then circulates in the loop for N clock cycles

Conversion takes N cycles with one bit resolved in each T

clk

Sample

modeSlide3

Modified Binary Search–

3 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

If V

< VFS/2, then b

j = 0, and Vo = 2*VXIf VX > VFS/2, then b

= 1, and V

= 2*(V

X-VFS/2)Vo is called conversion “residue”

ConversionmodeSlide4

Modified Binary Search–

4 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Constant threshold (V

/2) is used for each comparisonResidue experiences 2X gain each time it circulates the loopSlide5

Loop Transfer Function–

5 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Comparison → if V

< VFS/2, then b

j = 0; otherwise, bj = 1Residue generation → Vo = 2*(VX - bj*V

/2)

Slide6

Algorithmic ADC–

6 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Hardware-efficient, but relatively low conversion speed (bit-per-step)

Modified binary search algorithm

Loop-gain (2X) requires the use of a residue amplifier, but greatly simplifies the DAC → 1-bit, inherently linear (why?)

Residue gets amplified in each circulation; the gain accumulated makes the later conversion steps insensitive to circuit noise and distortionConversion errors (residue error due to comparator offset and/or loop-gain non-idealities) made in earlier conversion cycles also get amplified again and again – overall accuracy is usually limited by the MSB conversion stepRedundancy is often employed to tolerate comparator/loop offsets

Trimming/calibration/ratio-independent techniques are often used to treat loop-gain error, nonlinearity, etc.Slide7

– 7 –

Data Converters Algorithmic ADC Professor Y. ChiuEECT 7327 Fall 2014

Offset and RedundancySlide8

Offset Errors–

8 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Ideal

RA offset

CMP offset

= 2*(V

j*VFS/2)

→

/2 + V

/2Slide9

Redundancy (DEC, RSD)

– 9 –

Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

1 CMP

3 CMPsSlide10

Loop Transfer Function–

10 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Original

w/ Redundancy

Subtraction/addition both required to compute final sum

4-level (2-bit) DAC required instead of 2-level (1-bit) DACSlide11

Comparator Offset–

11 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Max tolerance of comparator offset is

FS/4 → simple comparatorsSimilar tolerance also applies to RA offset

Key to understand digital redundancy:Slide12

Modified 1-Bit Architecture

– 12 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

1-b/s RA transfer curve

w/ no redundancy

One extra CMPadded at VR/2Slide13

From 1-Bit to 1.5-Bit Architecture

– 13 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

A systematic offset –V

/4introduced to both CMPs

A 2X scaling is performedon all output bitsSlide14

The 1.5-Bit Architecture–

14 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

3 decision levels

→ ENOB = log

23 = 1.58Max tolerance of comparator offset is ±V

R/4An implementation of the Sweeny-Robertson-Tocher (SRT) division principleThe conversion accuracy solely relies on the loop-gain error, i.e., the gain error and nonlinearityA 3-level DAC is required

Can this technique be applied to SA ADC?Slide15

The Multiplier DAC (MDAC)

– 15 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

2X gain + 3-level DAC + subtraction all integrated

A 3-level DAC is perfectly linear in fully-differential form

Can be generalized to n.5-b/stage architecturesSlide16

A Linear 3-Level DAC–

16 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

b = 0

b = 1

b = 2Slide17

Alternative 1.5-Bit Architecture

– 17 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Ref

E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully digital correction of monolithic pipelined ADC’s,” IEEE Trans. on Circuits and Systems II, vol. 42, issue 3, pp. 143-153, 1995.

How does this work?Slide18

Error Mechanisms of RA–

18 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Capacitor mismatch

Op-amp finite-gain error and nonlinearity

Charge injection and clock feedthrough (S/H)

Finite circuit bandwidthSlide19

RA Gain Error and Nonlinearity

– 19 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Raw accuracy is usually limited to 10-12 bits w/o error correctionSlide20

Static Gain-Error Correction

– 20 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Analog-domain method:

Digital-domain method:

Do we need to correct for

error?Slide21

RA Gain Trimming–

21 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Precise gain-of-two is achieved by adjustment of the trim array

Finite-gain error of op-amp is also compensated (

not nonlinearity)

C1/C2 = 1 nominallySlide22

Split-Array Trimming DAC–

22 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Successive approximation utilized to find the correct gain setting

Coupling cap is slightly increased to ensure segmental overlap

8-bit gain

1-bit signSlide23

Digital Radix Correction–

23 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

Unroll this:Slide24

References–

24 –Data Converters Algorithmic ADC Professor Y. Chiu

EECT 7327

Fall 2014

P. W. Li, M. J. Chin, P. R. Gray, and R.

Castello

, JSSC, pp. 828-836, issue 6, 1984.C. Shih and P. R. Gray, JSSC, pp. 544-554, issue 4, 1986.H. Ohara et al., JSSC, pp. 930-938, issue 6, 1987.H. Onodera, T. Tateishi, and K. Tamaru, JSSC, pp. 152-158, issue 1, 1988.

S. H. Lewis et al., JSSC, pp. 351-358, issue 3, 1992.B. Ginetti et al., JSSC, pp. 957-964, issue 7, 1992.H.-S. Lee, JSSC, pp. 509-515, issue 4, 1994.

S.-Y. Chin and C.-Y. Wu, JSSC, pp. 1201-1207, issue 8, 1996.

E. G.

Soenen

and R. L. Geiger, TCAS2, pp. 143-153, issue 3, 1995.

I. E. Opris, L. D.

Lewicki, and B. C. Wong, JSSC, pp. 1898-1903, issue 12, 1998.O. E. Erdogan, P. J. Hurst, and S. H. Lewis, JSSC, pp. 1812-1820, issue 12, 1999.