Klinefelter ECE 7332 Spring 2011 Digitally Controlled Oscillators DCO Basic Topology of All Digital PLLs ADPLL Where does the DCO fit in Early Architectures Oscillator Background Current Research ID: 264955
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Slide1
Alicia KlinefelterECE 7332Spring 2011
Digitally Controlled Oscillators (DCO)Slide2
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer
CMOS ProcessHysteresis Delay Cell [9]A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC
ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuningComparison of Results
Outline
2Slide3
Problems with analog implementationDesign and verificationSettling time
20 – 30 ms in CPPLLs
10 ms in the ADPLLImplementation costCustom blocksLoop FilterHigh Leakage current
Large capacitor (2) areaCharge PumpLow output resistanceMismatch between
charging current and discharging current Phase offset and reference spurs
Why are ADPLLs useful?3Slide4
All-digital PLL (ADPLL) TOPOLOGY
Time-to-Digital
Converter (TDC)
Digital Loop Filter
Divider
ref(t)
DCO
out(t)
4Slide5
Architectures
Delay chain structure sets resolution
Mismatch causes linearity issues
Resolution: want low quantization noise
5
ADPLL:
Time-to-digital converter
Time-to-Digital
Converter (TDC)
Digital
Loop Filter
Divider
ref(t)
DCO
out(t)
div(t)
[1,
Perrott
]Slide6
Compact areaInsensitive to leakage
6ADPLL:
DIGITAL LOOP FILTER
Time-to-Digital
Converter (TDC)
Digital Loop Filter
Divider
ref(t)
DCO
out(t)Slide7
ADPLL: DCO
Time-to-Digital
Converter (TDC)
Digital
Loop Filter
Divider
ref(t)
DCO
out(t)
7
Replaces the VCO from analog implementations
Consumes 50-70% of overall ADPLL power
Generally consists of a digital controller implementing frequency acquisition algorithm and oscillator.Slide8
Power Consumption @ Frequency Phase NoiseMeasured with respect to a frequency offset from the carrier
The units, dBm/Hz, define noise
power contained in a 1 Hz bandwidthJitterLSB Resolution (ps)
Tuning rangeNote: bit resolution is rarely mentioned
Does not seem to have drastic impact on tuning range8
METRICSSlide9
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
Outline
9Slide10
Straightforward approachDAC + VCOVaractors used initiallyProblem with varactors:
Capacitance not very linear with input voltage.
For digital tuning, need flat regions.10
EARLY ARCHITECTURES: ANALOG TUNING
[3,
Xu
]Slide11
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
Outline
11Slide12
Frequency determined by delay of the invertersEach stage provides phase shift where
Supply voltage
Easy to integrate
High phase noise → Not good for RF applicationsCurrent starved → high resolution, high static power due to current source
OSCILLATORS: Ring oscillator12
Slide13
Low phase noisedissipates
only
of the total energy stored during one cycle. Complicated layoutHigh area
OSCILLATORS: Lc
oscillator13
240um
[4, Thiel]Slide14
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
Outline
14Slide15
Weighted capacitor networks replaced varactorsConcept of fine and coarse tuning introducedCoarse (binary weighted) lacks monotonicity
Fine (unit weighted) has monotonicity but complex control15
NOVELTY: FULLY DIGITAL TUNINGSlide16
To increase resolution, many systems use ΣΔ modulators for dithering the input to the unit caps.Unit cap determines gain of DCO
Recall, ΣΔ modulators are oversampling converters and produces output pulses proportional to signal changes.
Quantization noise effectsPhase noise goes down as frequency increases
16TECHNIQUE :
dithering
[1, Perrott]Slide17
If you have an LTI system, the energy spectral density of the output is similar to an eigenvalue of the system.Since we go from discrete time to continuous time, this relationship can be expressed as:
17
NOISE ANALYSIS:
DITHERING
H(s)
x
[n]
y(t)
[1,
Perrott
]Slide18
Recall:
18
NOISE ANALYSIS:
DITHERING
[1,
Perrott
]Slide19
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
Outline
19Slide20
Many traditional delay lines are simple invertersChain of tri-state inverters in parallelDriving capability modulation (DCM
)Changes the driving current of each delay cell by controlling number of enabled tri-state
buffers/inverters Bad power, linearityDELAY CELLS: DCM
20Slide21
Hysteresis delay cells (HDC) are relatively new in low power (2007 - ). Trade off power and delay resolution.Fewer needed to acquire the delay of a many traditional delay cells.
HDCs have wider operating rangeControl of driving current to obtain different propagation delay
DELAY CELLS: HYSTERESIS
21
[2]Slide22
Application: Wireless body area networksRelaxes phase noise requirementOscillator
structure based on a power-of-2 delay stage DCO (P2-DCO) architectureEach delay stages is ½ delay of
previous80um x 80um in 90nm CMOS5.4uW @ 3.4MHz, 1V supplyPresents two novel HDC topologiesImproves power-to-delay and area-to-delay ratios
22ImplementationSlide23
Uses different hysteresis cells for different tuning stages
Need for decoder removed due to power of two delay
Header and footer rarely turned on at same timeLeads to voltage scaling of the cell with hysteresis
23
Implementation: DELAY CELLS
[9]
[9]Slide24
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuningComparison of Results
Outline
24Slide25
As technology migrates, push towards standard cell implementations for portability.Goal: implement DCO in HDLRing oscillators always used for
synthesizeable DCOLimits implementation optionsMost delay cells inverters and NANDs
Controllers simply digital logicArchitecture: STANDARD CELL
25Slide26
Segmented delay line, hysteresis delay cells, and uses standard cells: ultra portable!140uW (@200 MHz) with 1.47-ps resolution
Segmented delay line power gating saves ~25-75% of powerDependent on operating frequency
26PAPER HIGHLIGHTS
[2]Slide27
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A
100μW, 1.9GHz oscillator with fully digital frequency
tuning
Comparison of Results
Outline
27Slide28
New DCO tuning word (OTW) presetting technique to reduce settling timeThree stages in ADPLL
PVT calibrationFrequency AcquisitionTracking (locked)Each mode is a search algorithm, each has its own scheme
For ring oscillator, controller implemented in digital logicFor LC oscillator, controller is capacitor bank28
CONTROLLER: LOCKING TIMESlide29
Paper [4] designed a new, faster locking algorithm for frequency acquisition.Locks in 18 clock
cyclesBinary search typically used
29CONTROLLER: FASTER ALTERNATIVE
[4]Slide30
PFD produces gain and fast/slow pulseMux selects fast/slow gain value
Gain value like the charge pump
As DCO frequency differs more from target, gain increasesUse previous gain with new gain to determine new guess value30
CONTROLLER: FASTER ALTERNATIVE
[4]Slide31
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuningComparison of Results
Outline
31Slide32
1.9 GHz DCO in 0.13um technology2 x 2mm2 using 6 metal layersSupply voltage at 0.5V, 100uW power
More device transconductance
(gm) is available for a given bias currentApplication: frequency synthesizer in wireless transceiverBetween calibration, oscillator runs free until next tuning cycle (TX/RX)
Other circuitry turned offNo external components used (even with LC oscillator)
32NOVELTY: SUBTHRESHOLDSlide33
Differential NMOS only for high output swing for low input voltagesInductanceWant high Q determines overall Q of system, startup current, and power consumption
Used bondwire
inductancesWant 1fF LSB from caps, but a problem when wiring parasitics on same order of magnitude
33OSCILLATOR: LC Based
[10]Slide34
Capacitor matching a problem for small unit capacitorsVaractors could workNeed flat areas of curve
Testing required to find input voltages of such areasSwitched capacitor implementation using linear capacitors proposedRouting parasitics reduced
34CHALLENGE:
SMALL CAPACITORS
Change in C
in by ΔC:
[10]Slide35
Basic Topology of All Digital PLLs (ADPLL)Where does the DCO fit in?
Early ArchitecturesOscillator
BackgroundCurrent ResearchSeminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-
submicrometer CMOS ProcessHysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN ApplicationsPortability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for
SoC ApplicationsFrequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCOSubthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
Outline
35Slide36
Power
Op. Freq
Voltage5.4uW3.4MGHz
1 V5.2uw3.89MHz1 V
8mW12.3MHz1.2 V
1.7mW20MHz1 V166uW163.2MHz1 V140uW200MHz1 V
110uW
200mhZ
0.8 V
75.9uW
239.2MHz
1 V
340uW
450MHz
1.8 V
1.7mW
560MHz
1.2 V
2.3mW
800MHz
0.9 V
23.3mW
1GHz1.8 V
5.5mW5.6GHz0.7 V
36
DESIGN COMPARISONS:
POWERSlide37
37
DESIGN COMPARISONS:
FREQ OFFSETSlide38
38
DESIGN COMPARISONS:
TUNING RANGESlide39
CPPSIM Tutorials[1, Perrot] PLL Digital Frequency Synthesizers
[2, Perrot] PLL Voltage Controlled Oscillators
All papers in the bibliography section of Wiki were used for plot generationPapers [2], [4], [9], [10], [14] addressed in presentation[3, Xu
] Xu, L. (2006, May 18). Digitally controlled oscillator. Retrieved from http://www.ecdl.tkk.fi/education/4198/pdf/dco_lxu.pdf
[4, Thiel] Thiel, B.T.; Neyer, A.; Heinen, S.; , "Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS,"
Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D. , vol., no., pp.228-231, 12-17 July 2009.39RESOURCESSlide40
Move to digital PLL implementations motivated by SoC applicationsNew digital circuits in ADPLL: TDC, filter, DCO
Ring oscillators versus LC oscillatorsCurrent ResearchInitial digital tuning with sigma-delta dithering
Delay cellsPortabilityFrequency acquisition algorithmSub-threshold operation
QUESTIONS?
40
Overview