/
Electronics  for   Physicists Lecture  14 Sequential   Logic Electronics  for   Physicists Lecture  14 Sequential   Logic

Electronics for Physicists Lecture 14 Sequential Logic - PowerPoint Presentation

sherrill-nordquist
sherrill-nordquist . @sherrill-nordquist
Follow
342 views
Uploaded On 2019-10-31

Electronics for Physicists Lecture 14 Sequential Logic - PPT Presentation

Electronics for Physicists Lecture 14 Sequential Logic November 2018 Electronics for physicists Marc Weber KIT Logic with feedback Feedback in digital circuits can store state lead to unable states ID: 761621

weber flip state flop flip weber flop state kit november electronics physicistsmarc 2018electronics physicists 2018 marc states clocked output

Share:

Link:

Embed:

Download Presentation from below link

Download Presentation The PPT/PDF document "Electronics for Physicists Lecture 1..." is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.


Presentation Transcript

Electronics for Physicists Lecture 14Sequential Logic

November 2018Electronics for physicists Marc Weber - KITLogic with feed-back Feed-back in digital circuits can: store state lead to unable states

November 2018Electronics for physicists Marc Weber - KITSequential logic Sequential logic is the combination of combinational logic with memory. The output state depends on the current input states and on previous input or output states. S imple sequential logic devicesflip-flopcounter shift register C omplex sequential logic devices Finite state machines (FSM)

RS flip-flopNovember 2018 Electronics for physicistsMarc Weber - KIT 2 inputs, 2 outputs Labeling of and is irritating, but useful. R = reset: R = 1 ( = 0)  Q = 1 S = set: S = 1 ( = 0)  Q = 0 R = S = 1 ( = = 0) is forbidden state.Transition to = = 1 preserves previous state.   truth table for RS flip-flop

RS flip-flopNovember 2018 Electronics for physicistsMarc Weber - KIT Why is R = S = 1 and = Q forbidden? R = S = 1 makes no sense. (Why set and reset at the same time?)(Don´t brake and accelerate your car simultaneously while driving!) = 1 and Q = 1 are not orthogonal. When moving from R = S = 1 to R = S = 0, result is unpredictable could be either of = 1, Q = 0 or = 0, Q = 1  

Clocked RS flip-flop November 2018Electronics for physicistsMarc Weber - KIT clocked RS flip-flop truth table for clocked RS flip-flop . x = any state one additional input C (clock) I f C = “0”, previous state is maintained, otherwise identical to non-clocked RS flip-flop. ( Recall NAND ≙ 0  1 gate ) What is the clock good for ? Why is most digital electronics clocked?

November 2018Electronics for physicists Marc Weber - KITBistable Multivibrator Note the cross-coupled transistors Note the hierarchy of resistor values R = S = 1 is not well-defined This is a simple latch and memory cell .

November 2018Electronics for physicists Marc Weber - KITD flip-flop From RS flip-flop to D flip-flop Forbidden state is eliminated !

D flip-flopNovember 2018 Electronics for physicistsMarc Weber - KIT clocked D flip-flop truth table for clocked D flip-flop . x = any state circuit symbol of clocked D flip-flop

Edge-triggered D flip-flop November 2018Electronics for physicistsMarc Weber - KIT input and output states of triggered D flip-flop as a function of time circuit symbol triggered D flip-flop Output Q S changes during clock transition fromC = “0”  “1” only.Why is this so ? Master Slave Q M Q s

Shift register November 2018Electronics for physicistsMarc Weber - KIT A shift register is a chain of transparent flip-flops , sharing the same clock.The output of flip-flop (i) is transferred to the input of the next flip-flop (i+1) and stored. Why is data to input flip-flop not instantly shifted to output flip-flop ?

Shift register November 2018Electronics for physicistsMarc Weber - KIT E xample : data sequence “1101”LSB first, MSB last!The initial state of the shift register be “0000” . 4 clock cycles are needed to transfer the bit sequence into the SR flip-flops 1 to 4.Shift register truth table

Trigger basics (ATLAS) Lot’s of data!! Raw data before L1 trigger: ~10 Pbyte/sec L1 L2 L3 LEVEL 1 Input rate: ~ 1 GHz (40 MHz x 25 events) Accept rate: 75 KHz  130 Gbyte/sec Processing time: ~2 µsec; Latency: 2.5 µsec Technologies: Electronics/Firmware LEVEL 2 Accept rate: 2 KHz  1.3 Gbyte/sec Processing Time: ~40 ms  Region of Interests Technologies: Firmware, Software/Networks Event Filter Accept Rate: 200 Hz  u p to 400 Mbyte/sec Processing Time: ~4 sec Technologies: Software/Networks Electronics for physicists November 2018

Digital pipelines at LHC November 2018Electronics for physicistsMarc Weber - KIT R aw data volume of the ATLAS SCT is Pb /s (≈ 6M ch. x 40 MHz x a few bits/ch.)Zero-suppression and data compression schemes reduce this by a factor of ≈ 100 A 132-cell pipeline provides 132 x 25 ns = 3.3 μs of latency for the L1 trigger decision Note the second pipeline, the derandomizing buffer (3 x 8 events deep)

Toggle flip-flop November 2018Electronics for physicistsMarc Weber - KIT Toggle flip-flop acts as a frequency divider T = “ 1” corresponds to circuit on the left . For T = “0”, D is connected internally to .  

Pattern recognition with a SR November 2018Electronics for physicists Marc Weber - KIT This circuit recognizes the bit sequence “1101” in an arbitrary string of data. Note that this requires to access each FF in parallel.

Ring counterNovember 2018 Electronics for physicistsMarc Weber - KIT Initializing the FFs with “1000”, the counter counts through the states: “1000”, “0100”, “0010”, “0001” and then starts again … Can we do better than 4 states with four FFs ?

Johnson counterNovember 2018 Electronics for physicistsMarc Weber - KIT What is different from the simple ring counter ? When initializing the FFs with “1000”, the Johnson counter produces 8 states .

State diagram of a 2-bit SRNovember 2018 Electronics for physicistsMarc Weber - KIT We have 4 states (Z 1 – Z 3 ) corresponding to the content of the SR Depending on the value of the new bit (nb) to move into the SR, the state Z is changed or not.We introduce the variables A1A 0 to indicate the old content of the SR, N1N 0 to indicate the new content, and the output variables Q 1 Q 0 (with Q 1 Q 0 = A 1 A 0) .

A 1 From state diagram, to state table, to state equation November 2018 Electronics for physicists Marc Weber - KIT nb To reconstruct N 0 from A 0 , A 1 and nb , use sum of products A0

November 2018Electronics for physicists Marc Weber - KITPattern recognition Trigger pattern: 1 0 1 # of hits 0 0 x 0 1 0 0 1 Actual patterns: 1 1 x 1 0 1 x 2 1 0 1 3 Recognize pattern “101” FIFO – first in, first out

Patter recognition of “101” with a SRNovember 2018 Electronics for physicistsMarc Weber - KIT We have 4 states (Z 1 – Z 3 ) depending on the number of matching bits in the SR The output variable Q0 indicates if a pattern matches (Q0 = “1”) or not (Q0 = “0”).

State table and equation November 2018 Electronics for physicists Marc Weber - KIT # of hits: decimal and binary

From state diagram, to state table, to state equation November 2018 Electronics for physicists Marc Weber - KIT