Mesochronous clocking and communication in onchip networks Daniel iklund Dept
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Mesochronous clocking and communication in onchip networks Daniel iklund Dept

of Electrical Engineering Link57590ping University S581 83 Link57590ping Sweden danwiisy liuse ABSTRACT Onchip networks ar becoming popular esear ch topic both in industry and universities Many e sear chers assume fully synchr onous or globally asyn

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Mesochronous clocking and communication in onchip networks Daniel iklund Dept

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Mesochronous clocking and communication in on-chip networks Daniel iklund Dept. of Electrical Engineering Linkping University S-581 83 Linkping, Sweden danwi@isy ABSTRACT On-chip networks ar becoming popular esear ch topic, both in industry and universities. Many e- sear chers assume fully synchr onous or globally asynchr onous, locally synchr onous model of opera- tion for the network. have pr eviously pr oposed the use of mesochr onous communication within the network as simple and obust way to get ar ound the pr oblems of fully synchr onous

operation. The mesochr onous communication technique is simple both in understanding and implementation and allows for signicant fr eedom in design, place- ment, and inter -subsystem delays. This paper pr esents the concept of mesochr onous communication and clocking. It further intr oduces possible implementation for the network component inter connections using mesochr onous communication with an integrated clock distribution mechanism. This implementation is then analyzed fr om functional perspective. 1. INTRODUCTION During the last few years ther has been signi- cant incr

ease in popularity of esear ch on on-chip net- works. ith many ar chitectural pr oposals ther ar also the need to understand the method of commu- nication within the network on lower levels. com- mon assumption is that the network is un either glob- ally synchr onously over the chip or that it is un com- pletely asynchr onously [1 2]. In principle ther ar thr ee methods to use for syn- chr onization of system. The most commonly used today is the synchr onous system wher global clock is distributed over the system with low skew This Daniel iklund is Ph.D. student at the division of Computer

Engineering, Dept of Electrical Engineering, Linkping University This work is funded by the STRINGENT electr onics center This work is based on an idea by Pr of. Christer Svensson, Electr onic De- vices, Dept of Electrical Engineering, Linkping University clock is then used to time all the events and transac- tions in the system. Another method that is popular in esear ch and ex- tr eme low power pr oducts is to un the system com- pletely asynchr onous. Completely asynchr onous sys- tems need to use handshaking or special timing cir cuitry for both computations and

communications in or der to keep synchr onization within the system. The thir method is to use blocks that ar syn- chr onous but communicate asynchr onously better known as the globally asynchr onous, locally syn- chr onous (GALS) methodology ith the curr ent in- cr ease in the number of dif fer ent clock domains used on single chip this is very pr omising overall tech- nique to use for IP block integration. If subsystem is distributed over lar ge ar ea within chip ther is also the possibility to use method that is somewhat in between the pr eviously men- tioned methods. Her ther is common

clock that is distributed to the system without concern about the phase dif fer ence in dif fer ent parts of the system. Parts of the system may un as synchr onous subsys- tems and can be designed using the accepted standar methods of today The communication between the subsystems is then done in much the same way as for fully synchr onous system. The primary dif fer ence is that the incoming data to subsystem has to be aligned to the local clock phase. Since the clock rate is the same for the entir system this can be performed with simple etiming cir cuitry have pr eviously pr oposed an

on-chip network [3] and suggested it should use mesochr onous com- munication and clocking scheme for internal commu- nication [4 ]. This paper pr esents possible solution for the mesochr onous communication and clock dis- tribution between the network components.
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NI NI NI NI Router Router Router Router IP block IP block IP block IP block Link Link Fig. Section of mesh style on-chip network. 2. CLOCK DISTRIBUTION IN ON-CHIP NETWORKS Assuming that the components of the on-chip net- work is implemented using method that is not fully asynchr onous, clock is needed in each outer

and network interface. If the system is to use glob- ally synchr onous model the distributed clock has to have low skew between the connected neighbors in the network but it is possible to allow signicantly mor clock skew acr oss longer distances in the net- work. Since ther ar only fairly local links in the net- work, see gur 1, this is feasible solution for net- works with low clock rate (up to few hundr ed MHz). fully asynchr onous solution of course do not need clock distribution at all. Ther is also the pos- sibility to use mixed system based on the glob- ally asynchr

onous and locally synchr onous (GALS) scheme, i.e. the outers and network interfaces ar un synchr onous internally and asynchr onous exter nally This method equir es the distribution of clock to every network component but ther is no specic demands on clock skew or even dif fer ence in clock fr e- quency between the components. 3. MESOCHRONOUS CLOCKING Our pr oposed solution is to use mesochr onous clock- ing, i.e. using the same fr equency but with unknown phase. Ther ar two basic methods for communica- tion between subsystems when using mesochr onous clocking. The rst is to

ecognize and handle the situ- ation when metastable conditions may occur [5 ]. The detection of this kind of possibly metastable condi- 16 Data Frame Reverse ctrl Reverse ctrl Frame Data 16 Two links Network component Network component Fig. Basic signals for one undir ectional internal net- work link. tion gives rise to 180 degr ee shift in the local clock phase used for synchr onizing the incoming data. This method has the advantage of not needing any extra wiring for the synchr onization but is bad since the clock phase dif fer ence may be very close to wher the metastable conditions will

occur The second appr oach is to keep as far away fr om the metastable case by analyzing the incoming data phase or by pr oviding timing signal along with the data signals that can be used to estimate the phase dif fer ence. One of the most basic equir ements for uncon- strained mesochr onous clocking and communication is that ther must be no special timing equir ements on the communication. This means that things like low level ow contr ol for the communication may be impossible to implement. The subsystems then have to be designed in such way that this low level ow contr ol

is not necessary pr opose to use the second appr oach wher ev- ery network component is built using the well-known methodology for fully synchr onous systems but with special interface cells for synchr onization at each in- put. 4. POSSIBLE IMPLEMENT TION OF MESOCHRONOUS CLOCKING In the SoCBUS pr oject every (unidir ectional) link fr om network component to another consists of data bus that is typically 16 bits wide, one forwar framing sig- nal, and two everse contr ol signals, as shown in g- ur 2. enable the use of mesochr onous clocking this link is then supported by single str obe

signal go- ing in the forwar dir ection. This str obe carries sig-
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Data Strobe clk1 Fig. Sender for str obed mesochr onous clocking. nal that is simply the clock fr equency divided by two. This signal will have the same characteristics when it comes to spr eading and distortion as the other signals transferr ed on the data and contr ol wir es. This str obe can then comfortably be used to time the transfers. As can be seen in gur 2, ther ar two signals, the e- verse contr ol, going in the opposite dir ection. When- ever ther ar two opposing unidir ectional links be-

tween the components as in the gur ther is no extra cost for these everse contr ol signals. They can simply be timed to the opposing forwar signals. This situa- tion is pr obably the by far most common but if ther is only one unidir ectional link between two components the everse contr ol signals have to be accompanied by their own str obe signal. As long as the data signal paths and the str obe sig- nal path is fairly well balanced in each link the str obe signal will convey all necessary information for the synchr onization to the local clock phase. Figur shows the sender side design

for mesochr onous link. The sender cr eates the str obe sig- nal associated with the link. The eceiver is somewhat mor complex, see gur 4. fr equency doubler is used to econstr uct the clock signal fr om the incom- ing str obe. This clock signal is eplica of the sender clock which is skewed to match the incoming data and is used for the latching of incoming data into the rst stage ip-ops. The second ip-op stage is used to time the data to the local clock phase. phase de- tector and phase comparator is used to select whether the second stage will

use the normal phase or the 180 degr ee shifted version of the local clock. ithout an extra ip-op stage to synchr onize the incoming data to the in-phase clock the signals fr om this second stage may have only one half clock cy- cle until the next rising edge in the eceiving network component. This half period can be used as timing Frequency doubler Phase comparator Data Strobe clk1* clk2 Data* DataO Fig. Receiver for str obed mesochr onous clocking. Data clk1* Strobe clk2 DataO Td Data* Fig. Receiver waveform for mesochr onous trans- mission.  denotes the eceiver synchr

onization de- lay constraint for the rst stage in pipelined implemen- tation of the network component. If this is not accept- able an additional ip-op stage may be intr oduced to synchr onize the signals fully to the local clock phase. Since the str obe signal is transmitted along with the communication this can also be used to distribute the clock to the network components. This is achieved by using the doubled fr equency fr om one of the input links as the network component clock. Thus ther is no need for an additional clock distribution network and the specic

link interface wher the clock is taken do not need any mor stages for the synchr onization than the rst one.
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5. MESOCHRONOUS VS. ASYNCHRONOUS COMMUNICA TION The simplest way of designing the network compo- nents is to use fully synchr onous design methodol- ogy for the on-chip network. This is possible for the time being but will eventually (within few years) become impossible for high end chips. When this time is eached ther is basically two ways to go for the communication internal to the network, either to partly/fully asynchr onous or mesochr onous solu- tion.

Asynchr onous solutions have some advantages over mesochr onous solutions since the handshaking will dir ectly allow for link-level ow contr ol that is generally needed for networks using buf fering within the network components. Another advantage is that good implementation of the asynchr onous interfaces will pr ovide an extr emely eliable system. The mesochr onous scheme in turn has some advantages over the asynchr onous solution. mesochr onous system can, fr om high perspective, be viewed as fully synchr onous system with pipeline delays on the inter connect links. The thr oughput

on every link can also be higher since ther is no need for handshaking of every transfer Thus the wir es may carry several sequential waves of data at the same time. The str obe signal used for synchr onization can be used to distribute the clock as well as conveying timing information. Also the components for imple- menting the mesochr onous communication is simple, compact, and obust. In an on-chip network the mesochr onous communi- cation must be complemented by asynchr onous bridg- ing between the network clock domain and the IP block clock domains. This asynchr onous communica- tion is

then done within the network interfaces. Thus the complete on-chip network system is an implemen- tation of highly exible GALS style interface str uc- tur e. 6. CONCLUSIONS This paper shows the applicability of mesochr onous communication and clocking to on-chip networks. possible implementation for synchr onization and e- timing is pr esented together with basic comparison of the mesochr onous and asynchr onous styles of com- munication. 7. REFERENCES [1] K. Goossens, J. van Meerber gen, A. Peeters, and ielage, “Networks on silicon: Combining best- ef fort and guaranteed services, in

Pr oceedings of the Design and est in Eur ope confer ence (DA TE) 2002. [2] Sune Nielsen and Jens Spars, “Analysis of low- power SoC inter connection networks, in Pr oc of the Nor chip confer ence 2001. [3] Daniel iklund and Dake Liu, “Switched inter connect for system-on-a-chip designs, in Pr oc of the IP2000 Eur ope confer ence 2000. [4] Daniel iklund and Dake Liu, “SoCBUS: Switched network on chip for har eal time em- bedded systems, in Pr oc of the International Par- allel and Distributed Pr ocessing Symposium (IPDPS) April 2003. [5] Fenghao Mu and Christer Svensson, “Self-tested

self-synchr onization cir cuit for mesochr onous clocking, IEEE ransactions on Cir cuits and Sys- tems vol. 48, no. 2, pp. 129–140, 2001.