Reinier A van Mourik MSc PhD Researcher Spintronics Devices IBM Eindhoven University of Technology IBM Almaden Research Center 650 Harry Rd San Jose CA 95120 USA Tel 1 408 927 2501 ID: 240444
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Slide1
Contact
Reinier A. van Mourik, MSc
PhD Researcher
Spintronics
Devices
IBM / Eindhoven University of Technology
IBM
Almaden
Research Center
650 Harry Rd
San Jose, CA 95120
USA
Tel +1 408 927 2501
Fax +1 408 927 2510
Mobile +1 408 821 4559
rvmourik@us.ibm.comSlide2
Reliability of Signal Propagation in Magnetostatically
Coupled Arrays of Magnetic
Nanoelements
Reinier van Mourik1,2, Li Gao1, Brian Hughes1, Charles Rettner1, Bert Koopmans2, Stuart Parkin1
1. IBM
Almaden
Research Center, San Jose, CA
2. Eindhoven University of Technology, Eindhoven, the NetherlandsSlide3
1. Introduction
Nanomagnetic
logic - principle
Energy-efficientNon-volatileFastRadiation resistantMajority gate
A
B
D
C
M
A
B
C
D
M
Majority gate is programmable NAND/NOR gate
Full logic set
output readSlide4
1. Introduction
Outline
Experiment and simulation:
inherent unreliabilityAlternative for conventional NML: Domain wall clockingSlide5
2. Error rate in NML devices
Experiment setup
fabrication
measurementArtificial input biases first dot according to reset direction
~70Oe
d514
MFM shows state of each dot
The RH curve of the MTJ shows output of deviceSlide6
2. Error rate in NML devices
Single device: shot-to-shot results
Output MTJ state alternates accordingly when alternating input direction.
input
outputSlide7
2. Error rate in NML devices
Many devices: device-to-device results
Success/error is highly reproducible, thus inherent in device.
68/158 (43%) of devices contain errors
repeat clocking cycle, input +x
clocking cycle, input +x
clocking cycle, input -x
1
16/123 (94
%) of devices evolve to exact same state
66/79
(
84%) of devices evolve to exact inverse state Slide8
2. Error rate in NML devices
Error rate in signal propagation - simulations
Device-to-device error rate tends to 50% as length increases
Last NM evolves before signal reaches itErrors are caused by last magnet evolving early.Slide9
3. Domain wall clocking
Domain wall clocking - principle
Fringing field from domain wall in perpendicularly magnetized material can reset
nanomagnets.Slide10
3. Domain wall clocking
DW clocking – experimental setup
PMA nanowire 60-180nm
wide Domain wall injection line
Hall bar
nanodots
Py
60x90x20nm
AMR read
hall bar read
DW
1. inject
DW
2. propagate
DW by H field
3. read
resistance change in AMR and Hall barSlide11
3. Domain wall clocking
DW clocking
- results
Prepare device in incorrect statePass DW underneath
End in correct state
DW clocking demonstrated in 1- and 2-magnet devicesSlide12
Conclusion
Nanomagnetic
Logic is magnetic alternative to CMOS logic
Analysis done of reliability of NML devices with integrated outputErrors are reproducible per device and tend to 50% among devices.Domain Wall clocking is demonstrated as alternative clocking scheme
slides & contact
:
http://
tinyurl.com/RvM-IBM