E85 Digital Design amp Computer Engineering Finite State Machines Lecture 4 Breaks cyclic paths by inserting registers Registers contain state of the system State changes at clock edge system ID: 1031522
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1. Lecture 4: Finite State MachinesE85 Digital Design & Computer Engineering
2. Finite State MachinesLecture 4
3. Breaks cyclic paths by inserting registersRegisters contain state of the systemState changes at clock edge: system synchronized to the clockRules of synchronous sequential circuit composition:Every circuit element is either a register or a combinational circuitAt least one circuit element is a registerAll registers receive the same clock signalEvery cyclic path contains at least one registerTwo common synchronous sequential circuitsFinite State Machines (FSMs)PipelinesSynchronous Sequential Logic Design
4. Consists of:State registerStores current state Loads next state at clock edgeCombinational logicComputes the next stateComputes the outputsFinite State Machine (FSM)
5. Next state determined by current state and inputsTwo types of finite state machines differ in output logic:Moore FSM: outputs depend only on current stateMealy FSM: outputs depend on current state and inputsFinite State Machines (FSMs)
6. Traffic light controllerTraffic sensors: TA, TB (TRUE when there’s traffic)Lights: LA, LBFSM Example
7. Inputs: CLK, Reset, TA, TBOutputs: LA, LBFSM Black Box
8. FSM State Transition DiagramMoore FSM: outputs labeled in each stateStates: CirclesTransitions: Arcs
9. Moore FSM: outputs labeled in each stateStates: CirclesTransitions: ArcsFSM State Transition Diagram
10. Current StateInputsNext StateSTATBS'S00XS1S01XS0S1XXS2S2X0S3S2X1S2S3XXS0FSM State Transition Table
11. Current StateInputsNext StateS1S0TATBS'1S'0000X01001X0001XX1010X01110X11011XX00StateEncodingS000S101S210S311FSM Encoded State Transition TableS'1 = S1 xor S0 S'0 = S1S0TA + S1S0TB
12. Current StateOutputsS1S0LA1LA0LB1LB0000010010110101000111001OutputEncodinggreen00yellow01red10FSM Output TableLA1 = S1LA0 = S1S0LB1 = S1LB0 = S1S0
13. FSM Schematic: State Register
14. FSM Schematic: Next State Logic
15. FSM Schematic: Output Logic
16. Multi-input XOR: Odd paritySystemVerilog Descriptionmodule trafficFSM(input logic clk, reset, input logic ta, tb, output logic [1:0] la, lb); logic [1:0] state, nextstate, sb; logic tab, tbb, p1, p2; // state register flopr #(2) statereg(clk, reset, nextstate, state); // next state logic not n0(sb[0], s[0]); not n1(sb[1], s[1]); not n2(tab, ta); not n3(tbb, tb); xor x1(nextstate[1], state[0], state[1]); and a1(p1, sb[0], sb[1], tab); and a2(p2, sb[0], s[1], tbb); or o1(nextstate[0], p1, p2); // output logic buf b1(la[1], s[1]); and a3(la[0], s[0], sb[1]); inv n4(lb[1], s[1]); and a4(lb[0], s[0], s[1]);endmodule
17. FSM Timing Diagram
18. Binary encoding: i.e., for four states, 00, 01, 10, 11One-hot encodingOne state bit per stateOnly one state bit HIGH at oncei.e., for 4 states, 0001, 0010, 0100, 1000Requires more flip-flopsOften next state and output logic is simplerFSM State Encoding
19. Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s on it. The snail smiles whenever the last two digits it has crawled over are 01. Design Moore and Mealy FSMs of the snail’s brain.Moore vs. Mealy FSM
20. Mealy FSM: arcs indicate input/outputState Transition Diagrams
21. Current StateInputsNext StateS1S0AS'1S'0000010010001001011101000110100StateEncodingS000S101S210Moore FSM State Transition TableS1’ = S0AS0’ = A
22. Moore FSM Output TableY = S1Current StateOutputS1S0Y000010101
23. Current StateInputNext StateOutputS0AS'0Y0010010010101101StateEncodingS00S11Mealy FSM State Transition & Output TableS0’ = AY = S0 A
24. Moore Mealy
25. Moore & Mealy Timing Diagram
26. Break complex FSMs into smaller interacting FSMsExample: Modify traffic light controller to have Parade Mode.Two more inputs: P, RWhen P = 1, enter Parade Mode & Bravado Blvd light stays greenWhen R = 1, leave Parade ModeFactoring State Machines
27. Unfactored FSMFactored FSMParade FSM
28. Unfactored FSM
29. Factored FSM
30. Identify inputs and outputsSketch state transition diagramWrite state transition tableSelect state encodingsFor Moore machine:Rewrite state transition table with state encodingsWrite output table5. For a Mealy machine: Rewrite combined state transition and output table with state encodings6. Write Boolean equations for next state and output logic7. Sketch the circuit schematicFSM Design Procedure