Smart pixels project using GF 0.13µm technology - PowerPoint Presentation

Slide1

Smart pixels project using GF 0.13µm technology

Patrick Pangaud

CPPM

24 July 2014

pangaud@cppm.in2p3.frSlide2

Hybrid Pixels Detector

for particles trackers

July 24, 2014

Meeting GF / CPPM P. Pangaud

2

An early 3-D approach!!

Sensor for particles detection

Dedicated electronic chipANDA fine pitch bump-bonding solder for interconnection

- Sensors

(Si, CdTe, GaAs, Diamond…) for ionizing particles - Electronic pixel readoutMonolithic deviceAnalog detection (low noise, low power)DiscriminatorDigital readoutSlide3

The "monolithic" pixels (integrated in the sensor chip = HVCMOS) is estimated

to

be 3x cheaper

than the conventional solution (hybrid pixels). The cost of IBL is estimated

to be 95

CH / cm ². (Atlas pixel week, November 4, 2013)

PHASE 1: No change for the ATLAS pixel, but the possibility to glue monolithic pixels on FEI4 for a new IBL layer = cheaper and more efficient. PHASE 2: Full monolithic pixels, less expensive with better efficiency. If the HVCMOS solution is really advantageous, then it should provide ATLAS + CMS (pixels + strips) or 240m ²!!!!

2008 : 1st version of the Front-End pixel

R&D program :

RD53 ( ATLAS et CMS)

HVCMOS

RD initiative

(

ATLAS et CMS)

2019 : 3rd version of the Front-End pixel

2014 : 2nd version of the Front-End pixel

Hybrid Pixels Detector

for particles trackers : upgrades

July 24, 2014

3

Meeting GF / CPPM P. PangaudSlide4

Smart pixel project

July 24, 2014

Meeting GF / CPPM P. Pangaud

4

From the Hybrid Pixel, the outer sensor is

placed now into the substrate

.

The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly inside n-well, NMOS transistors are situated in their p-wells that are embedded in the Deep-well as well.The best results are achieved when a standard high voltage and/or High Ohmic wafer CMOS technology is used. A lowly-doped deep n-well can be then used. Such an n-well can be reversely biased with a high voltage. We expect a large depleted area thickness The charge generated by ionizing particles in the depleted area is collected by drift. Due to high electric field and small drift path, charge collection is very fast.Due to drift based charge collection we

expect to get an high radiation tolerance

P-substrate

NMOS transistor

in its p-well

PMOS

transistor

in its n-well

Particle

E-field

Deep n-well

Pixel

electronics

in

the

deep

n-

well

The sensor is based on the “

deep” n-well in a p-substrateSlide5

Drift means to get the biggest depleted area

-> fast charges collection, more radiation hardness

The depletion (d) is proportional to

The equivalent charge collection is 80e-/µm

Example

The reality is a mixed of depletion and diffusion charge collected, maybe in-between

.

 Charge collection by drift (HV vs HR)July 24, 2014Meeting GF / CPPM P. Pangaud5 charges sharing Psub

DNWELL

NWELL

PWELL

DNWELL

NWELL

PWELL

reduced

charges sharing

Psub

DNWELL

NWELL

PWELL

DNWELL

NWELL

PWELL

10Ω.cm

gives d=15µm@100V

(800

e-)

3

kΩ.cm

gives d=50µm@10V

(4000

e-)Slide6

The HV2FEI4_GF Chip

July 24, 2014

Meeting GF / CPPM P. Pangaud

6

The CPPM has submitted

(June 2013) a new HV2FEI4 version in

GlobalFoundries

0.13µm BCDLite technology. The HV2FEI4 GF version is a 26 columns and 14 rows matrix pixels.The HV CMOS sensor pixels are smaller than the standard FEI4’s pixels chip, in our case 33μm x 125μm - so that three such pixels cover the area of the original pixel.

2

312

31

Bias A

Bias B

Bias C

FEI4 Pixels

CCPD Pixels

Signal transmitted

capacitively

The pixel chain contains charge sensitive amplifier, comparator and

tunable

DAC

.

The HV2FEI4_GF chip contains additional test structures

Test Transistors

:

3 NMOS ; 3 PMOS

Mini size :150n/130n

Narrow channel size : 200n/15µ

ELT size : 2,639µ/1.302µ

Pixels simple (outside of the matrix)

1 pixel chain without discriminator

(

Pixel_Alone

)

1

pixel

without

analog Front-End chain

(

Pixel_DNW

)

Additional Test

1 inner Current reference readout

1 DAC for test purpose Slide7

GF to FEI4A Communication

1

2

3

5

6

4

1

Investigate the FEI4 pixel “1”:

CCPD pixel “2”, “4” and “6” are

readen

with

different output amplitudeSlide8

TCAD

Simulation- a precious help

July 24, 2014

Meeting GF / CPPM P. Pangaud

8

By TCAD simulation, ~

4.8um

depletion depth is expected @Vsub

= -30V  384e (MIPs).Psub

10 ohms.cmDepletion width is ~1.5um @ Vsub= -30V. Due to the relative heavy doping in the p-region, large dead region exits between pixels. MEBES CRUISER APPLICATIONSlide9

Pixels behavior at 1GRads (outside of matrix)

July 24, 2014

Meeting GF / CPPM P. Pangaud

9

SR90

Pixel DNW

After

2hrs at 70°CSR90Pixel AloneAfter 2hrs at 70°CAfter 200MRads, the both signals were to weak to be check by a spectrum analysis.The preamplifier has a defect cascode transistor (

bad size) from the design. This cascode transistor, is not enough hardness for this High Level dose

. At 1GRads, the chip is still alive.Amplifier output vs. DoseSlide10

ELT

nmos

show good radiation hardness

up to 1GRad

Results of HV2FEI4_

GF chip

under X-Rays July 24, 2014Meeting GF / CPPM P. Pangaud10Mini nmos Vth reduces dramatically after 2 hours 70deg annealing at 800MRad. Accidental? Continue study needed!!

Test transistors available in the chip :

3 NMOS and 3 PMOS with the sizes :Mini : 150n/130nNarrow : 200n/15µ

ELT : 2,64µ/160nSlide11

How to enhanced

the HV2FEI4_

GF application

Our application is a little bit special because we want to apply a high voltage (negative value) directly on the substrate (

Psubstrate), and that's why all our Low Voltage transistors are designed inside the DNWELL, in order to isolate them…

We want to use the DNWELL/Psubstrate diode to collect charges from particles detection , that’s why we need :

to apply a (negative) voltage as high as possible to the Psubstrate,to have a depleted area as large as possible,to have the break-down voltage as high as possible.All these constraints apply here but also hereDNWELLPsubstrate

DNWELLPsubstrate

That’s why it is important for us to understand what is generated around the DNWELL area : Psubstrate, Pfield by auto-generation, or something else (?)…Because we want to avoid any generation of any highly doped area (as PFIELD) butted to the DNWELL. Psubstrate butted to the DNwell would be the best solution…July 24, 2014Meeting GF / CPPM P. Pangaud11Slide12

To increase the depleted zone , we need

HV

technology and High Resistivity waferTo enhanced the pixel architecture, by applying if possible

an isolated NWELL into the DNWELL (PWHV layer?)To increase the

reliability, we need to design a radiation hardness pixel structure.Can we tweak the design

rules to increase the BV, to avoid Punch Through effect and to optimize the S/N ratio.To increase the

detection efficiently (smaller pixel and higher S/N ratio), we need to understand the process generationBack-Metallization and

TSV approachTo increase the matrix surface, we need to increase the reticle size, by using stitching solution.Technology requirementsJuly 24, 2014Meeting GF / CPPM P. Pangaud12Slide13

Capacitive coupling and Monolithic pixels

Phase 1 (2017)

glued on FEI4Low noise electronic @300MRadssub-pixel pitch (actual 33x125 um, options 25x125 um, 50x50 um)1.5m²

production<1% bad /masked pixelPhase 2 (2020)New chip ( pixels and strips)

Low noise electronic @1000MRads10m² production (10m² pixels

+ 200m² Strips for ATLAS)Stitching solution

<1% bad /masked pixelProduction approach

July 24, 2014Meeting GF / CPPM P. Pangaud13Slide14

Which scheme to do prototyping

HR wafer and triple

wellLP vs BCDLite?

Full wafer delivering…Production time frame and large scale production

Partnership and communicationTechnology access and data results exchange

Conferences and papers visibility….Cost

Business and sales approach

July 24, 2014Meeting GF / CPPM P. Pangaud14