Products and specifications disc ussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice PDF document - DocSlides

Products and specifications disc ussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice PDF document - DocSlides

2014-12-06 175K 175 0 0

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Products are only warranted by Micron to meet Microns production data sheet specifications All information discussed herein is provided on an as is basis without warranties of any kind TN2961 Wear Levelin g in NAND Flash Memory Introduction PDF 0900 ID: 21497

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Presentations text content in Products and specifications disc ussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice


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Products and specifications disc ussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “as is” basis, without warranties of any kind. TN-29-61: Wear Levelin g in NAND Flash Memory Introduction PDF: 09005aef8467d996/Source: 09005aef8467d99e Micron Technology, Inc., reserves the right to change products or specifications without notice. tn2961_wear_leveling_in_nand.fm - Rev. G 4/11 EN 2011 Micron Technology, Inc. All rights reserved. Technical Note Wear Leveling in Micron NAND Flash Memory Introduction This document describes the recommended we ar leveling algorithm to be implemented in the flash translation layer (FTL) software for Micron NAND Flash memory. Wear Leveling and the Fl ash Translation Layer In Micron single-level cell (SLC) and multilevel cell (MLC)NAND Flash memory, each physical block can be programmed and erased reliably up to 100,000 and 10,000 times, respectively. For write-intensive applications, it is recommended to implement a wear leveling algorithm to monitor and spread the number of write cycles per block. In memory devices that do not use a wear leveli ng algorithm not all blocks get used at the same rate. The wear leveling algorithm ensures that equal use is made of all the available write cycles for each block. Wear leveling is implemented in the flash tran slation layer (FTL), wh ich is the additional software layer between the file system and the NAND Flash memory. The FTL allows operating systems to read and write to NAND Flash memory devices in the same way as disk drives and provides the tr anslation from virtual to physic al addresses. Wear leveling can also be implemented by the file system directly on the NAND Flash (see Figure 1). Refer to the data sheets for the full list of root part numbers and for further information on the devices (see “References” on page 5).
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PDF: 09005aef8467d996/Source: 09005aef8467d99e Micron Technology, Inc., reserves the right to change products or specifications without notice. tn2961_wear_leveling_in_nand.fm - Rev. G 4/11 EN 2011 Micron Technology, Inc. All rights reserved. TN-29-61 Wear Leveling in NAND Flash Memory Wear Leveling and the Flash Translation Layer Figure 1: Software Tool Chain fo r an Embedded Sy stem Using NAND Operating System File System Flash Translation Layer FTL interface Garbage Collection Wear Leveling Hardware Adaptation Layer Low Level Driver Error Correction Code Bad Block Management NAND Flash Device Operating System File System Wear Leveling Wear Leveling in the FTL Wear Leveling in the File System Hardware Adaptation Layer Low Level Driver Error Correction Code Bad Block Management NAND Flash Device
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PDF: 09005aef8467d996/Source: 09005aef8467d99e Micron Technology, Inc., reserves the right to change products or specifications without notice. tn2961_wear_leveling_in_nand.fm - Rev. G 4/11 EN 2011 Micron Technology, Inc. All rights reserved. TN-29-61 Wear Leveling in NAND Flash Memory Increasing the Lifespan of a NAND Flash Memory Device Increasing the Lifespan of a NAND Flash Memory Device This section shows how using wear leveling can increase the lifespan of a NAND Flash device. Lifetime Without Wear Leveling For systems that have a file allocation tabl e (FAT) based file system, the FAT table is always stored in the same virtual blocks. Frequent FAT table updates are required during data WRITE operations, which implies frequent erase cycles on the same physical blocks, hence a reduced NAND Flash lifetime. The following example calculates how many ti mes a FAT table (FAT32 and a cluster size of 2KB) is updated when writing a 10MB file to a NAND Flash memory with a physical erase unit of 16KB (NAND small page device). To write a file of 10MB, 5KB entries in FAT and 5KB clusters in the file system are required. This corresponds to 640 physical NAND Flash blocks. This means that the file can be written at the same location 20 times: This is greater than the maximum number of program/erase cycles. The expected NAND Flash lifetime can be calculated as follows: This means that if the applic ation writes at 3KB/s, the expected lifetime of the NAND blocks is: In a NAND Flash, when virtual blocks are ma pped to the same physical blocks, the life- time of the device is significantly reduced, independently of its size. Lifetime with Wear Leveling Wear leveling extends the lifetime of NAND Flash devices because it ensures that even if an application writes to the same virtual blocks over and over again, the PROGRAM/ ERASE cycles will be distributed evenly over the NAND Flash memory. For example, the expected lifetime of a 64 MB (512Mb) NAND Flash device can be calcu- lated as follows: In this example, 0.7 is the file system overhead. () ()
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PDF: 09005aef8467d996/Source: 09005aef8467d99e Micron Technology, Inc., reserves the right to change products or specifications without notice. tn2961_wear_leveling_in_nand.fm - Rev. G 4/11 EN 2011 Micron Technology, Inc. All rights reserved. TN-29-61 Wear Leveling in NAND Flash Memory Wear Leveling Algorithms Wear Leveling Algorithms Wear leveling is associated with a block aging table (BAT) to store information about which blocks have been erased in a selected period of time. There are two kinds of wear leveling that can be implemented in the FTL: • Dynamic wear leveling • Static wear leveling Dynamic Wear Leveling When applying the dynamic wear leveling, ne w data is programmed to the free blocks (among blocks used to store user data) th at have had the fewest WRITE/ERASE cycles. Static Wear Leveling With static wear leveling, the content of bl ocks storing static data (such as code) is copied to another block so that the original block can be used for data that is changed more frequently. Static wear leveling is triggered when the difference between the maximum and the minimum number of WRITE/ERASE cycles per block reaches a specific threshold. With this particular technique, the mean age of physical NAND blocks is maintained constant.
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8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. TN-29-61 Wear Leveling in NAND Flash Memory References PDF: 09005aef8467d996/Source: 09005aef8467d99e Micron Technology, Inc., reserves the right to change products or specifications without notice. tn2961_wear_leveling_in_nand.fm - Rev. G 4/11 EN 2011 Micron Technology, Inc. All rights reserved. References The following documents related to NAND Flash memory are available on www.micron.com • NANDxxx-A, single-lev el cell, small page, 528-byte/264 -word page, 3 V supply voltage, NAND Flash memory data sheets • NAND01G-B2B_NAND02G-B2C, single level cell, large page, 2112-byte/1056-word page, 1.8 V/3 V supply voltage, NA ND Flash memory data sheets • NANDxxGW3C2B, multilevel cell, large page, 2112-byte page, 3 V supply voltage, NAND Flash memory data sheets • Garbage collection in NAND Flash memory • Error Correction Code in Single-Level Cell NAND Flash Memory • Bad Block Management in NAND Flash Memory Conclusion Implementing wear leveling is recommended as part of the software tool chain (either in the FTL or file system) to increase the lifetime of NAND Flash in an embedded system. In addition, it is recommended that you implement garbage collection and bad block management algorithms. It is mandatory th at you implement error correction code algorithms. To help integrate NAND Flash memory in ap plications, Micron can provide a full range of software solutions, such as a file system , sector manager, drivers, and code manage- ment. Contact your Micron sa les representati ve or visit www.micron.com for more details.

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