PPT-Scalable Multi-Cache Simulation Using GPUs

Michael Moeng Sangyeun Cho Rami Melhem University of Pittsburgh Background Architects simulating more cores Increasing simulation times Cannot keep doing singlethreaded simulations if we want to see results in a reasonable time frame. Client sends HTTP request 2 Web Cache responds immediately if cached object is available 3 If object is not in cache W eb Cache requests object from Application Server 4 Application Server generates response may include Database queries 5 Applicatio Message Passing Sharedmemory single copy of shared data in memory threads communicate by readingwriting to a shared location Messagepassing each thread has a copy of data in its own private memory that other threads cannot access threads communicate using BU Shared Computing Cluster. Scientific Computing and Visualization. Boston . University. GPU Programming. GPU – graphics processing unit. Originally designed as a graphics processor. Nvidia's. Processors. Presented by . Remzi. Can . Aksoy. *Some slides . are. . borrowed from a ‘Papers We Love’ . Presentation. EECS 582 – F16. 1. Outline. The . Scalable Commutativity Rule: . Whenever interface operations commute, they can be implemented in a way that scales. Luis . Herranz. Arribas. Supervisor: Dr. José M. Martínez Sánchez. Video Processing and Understanding Lab. Universidad . Aut. ónoma. de Madrid. Outline. Introduction. Integrated. . summarization. Supercomputing. The Next wave of HPC. Presented by Shel Waggener. HP Materials from Marc Hamilton. June. , . 2011. © Copyright 2011 Hewlett-Packard Development Company, L.P.    . GPUs – changing the Economics of Supercomputing. Larry Peterson. In collaboration with . Arizona. , Akamai. ,. . Internet2. , NSF. , North Carolina, . Open Networking Lab, Princeton. (and several pilot sites). S3. DropBox. GenBank. iPlant. Data Management Challenge. Direct-mapped caches. Set-associative caches. Impact of caches on performance. CS 105. Tour of the Black Holes of Computing. Cache Memories. C. ache memories . are small, fast SRAM-based memories managed automatically in hardware. TLC: A Tag-less Cache for reducing dynamic first level Cache Energy Presented by Rohit Reddy Takkala Introduction First level caches are performance critical and are therefore optimized for speed. Modern processors reduce the miss ratio by using set-associative caches and optimize latency by reading all ways in parallel with the TLB(Translation Lookaside Buffer) and tag lookup. Mohammad . Sadrosadati. Amirhossein. . Mirhosseini. Seyed. . Borna. . Ehsani. Hamid . Sarbazi. -Azad. Mario . Drumond. Babak. . Falsafi. Rachata. . Ausavarungnirun. Onur. . Mutlu. Register file size limits GPU scalability . Iterative Local Searches. Martin . Burtscher. 1. and Hassan Rabeti. 2. 1. Department of Computer Science, Texas State University-San Marcos. 2. Department of Mathematics, Texas State University-San Marcos. Scientific Computing and Visualization. Boston . University. GPU Programming. GPU – graphics processing unit. Originally designed as a graphics processor. Nvidia's. GeForce 256 (1999) – first GPU. COS 418: Distributed Systems. Lecture . 14. Wyatt Lloyd. Consistency Hierarchy. Linearizability. Sequential Consistency. Causal+ Consistency. Eventual Consistency. e.g., RAFT. e.g., Bayou. e.g., Dynamo. Large scale computing systems. Scalability . issues. Low level and high level communication abstractions in scalable systems. Network interface . Common techniques for high performance communication.