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Bitslicing
Bitslicing

Bitslicing - PowerPoint Presentation

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Bitslicing - Description

using Smallscale Hierarchical Floorplanning Evan Vaughan Get RTL Compilier and SoC Encounter to place amp route a bitsliced datapath Began by modifyingreducing libraries ModifygtsynthesizegtPampR ID: 540271 Download Presentation

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hierarchical design place cells design hierarchical cells place black modules amp fences standard boxes flow module results floorplan script

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Presentation on theme: "Bitslicing"— Presentation transcript

Slide1

Bitslicing using Small-scale Hierarchical Floorplanning

Evan VaughanSlide2

Get RTL Compilier and SoC Encounter to place & route a

bitsliced

datapathBegan by modifying/reducing librariesModify>synthesize>P&RVery time consuming and no good results.

ReviewSlide3

Original approach involved far too much custom designAbandoned that.Focus has shifted to

floorplanning

Use hierarchical design methodologies to floorplanSince the last time…Slide4

Meant for large-scale designsBy default, Encounter only makes it available for larger designsBreaks design into manageable pieces when

floorplanning

Allows for parallel design of blocksHierarchical DesignSlide5

First must make a hierarchical designOriginal Kogge-Stone

verilog

completely flatModified verilog to make overall design hierarchical

ApproachSlide6

Synthesis Results

Flat Design

Hierarchical DesignSlide7

Hierarchical design yields no difference in P&R

Place & RouteSlide8

Uses partitions, modules, groups, fences, etc…Fence allows user to define spaces where standard cells will be placedCan specify modules as fences

Specify each bit module as a fence

Place fences in core as bitslicesPlace cells in fencesEncounter wasn’t showing my bits as modules

Hierarchical FloorplanningSlide9

ModulesSlide10

Defining black boxes creates instances of the modulesCan place modules by hand then place black boxes (Place>Standard Cells)Remove black boxes (

unspecifyBlackBox

–keepPtn)Removes black boxes but leaves fence behindCan then place standard cells within module fences.

Black Box FlowSlide11

PlacementSlide12

Kind of a hackCan’t unspecifyBlackBox from GUI

Multiple placements

Works fine as script but cumbersome in the GUICan ignore Black Box flow and directly specify fences in a script or in terminalStill no way for GUI-based flowFences do not show up in floorplan

view

ProblemsSlide13

By default, Encounter requires >100 cells for a module to be displayed after import.Design>Preferences>Display Min. Floorplan

Module Size to change this.

Alternatively “setPreference MinFPModuleSize 0” in a script/terminalCan easily place & resize modules into the core area

Define them as fencesPlace standard cells

GUI-based FlowSlide14

Very easily implemented as a scriptFences prevent cells from moving outside of assigned rowsOptimization can be run without destroying

bitslice

Easily integrated into any flowScriptingSlide15

ResultsSlide16

Final Layout (Pre-optimization)Slide17

Post-optimization (Timing)Slide18

Final

Layout (Post-optimization)Slide19

No previous ASIC designScriptingSynthesisPlace & Route

Verilog

Hierarchical Design methodologiesWhat I’ve LearnedSlide20

Questions?