FlybackApplication Note AN-16stability, etc. This presents an enorm - PDF document

FlybackApplication Note AN-16stability, etc.  This presents an enorm
FlybackApplication Note AN-16stability, etc.  This presents an enorm

FlybackApplication Note AN-16stability, etc. This presents an enorm - Description


June 1996 CM CHOKEVACCX VB TOPSwitch Output Capacitor Output Post Filter L C Bias CapacitorControl Pin Capacitor and Series Resistor SOURCECONTROL A 1 System Requirements VACMIN VACMAX fL VO ID: 510923 Download Pdf

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June 1996 CM CHOKEVACCX +-VB+ TOPSwitch Output Capacitor Output Post Filter

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June 1996 FlybackApplication Note AN-16stability, etc. This presents an enormous challenge involvingoptimize the design. The design method described belowdesign methodology. The step-by-step design procedure is a CM CHOKEVACCX +-VB+ TOPSwitch Output Capacitor Output Post Filter L, C Bias CapacitorControl Pin Capacitor and Series Resistor SOURCECONTROL A 1. System Requirements VACMIN, VACMAX, fL, VO, PO, h, Z B3. Determine CIN, VMIN4. Determine VOR, VCLO5. Determine DMAX6. Set KRP7. Determine IAVG, IP, IR, IRMS8. Choose TOPSwitchYN 9. Calculate TOPSwitch loss PD 10. PD Too HighNY To Step 12Step 1-2 Determine System Level Requirements and Choose Feedback Circuit11. IP= 0.9 x ILIMIT or KRP= 1 Step 3-11 Choose The Smallest TOPSwitch For The Required Power scope of this application note. However, such requirements areconverter configuration. The only part of the circuit configurationthat may change is the feedback circuitry. Depending on thepower supply output requirement, one of four possible circuits,shown in Figures 3-6, will be chosen for the application. flyback1.Determine system requirements and decide on feedback2.Find the smallest capable for the application.3.Design the smallest transformer for the chosen.4.Select all other components in Figure 1 to complete the 3 13. Choose Core & Bobbin Determine Ae, Le,AL, BW14. Set NS, L15. Calculate NP, NBY S, L Iterated M To Step 25Step 12-24 Design The Smallest Transformer To Work with The TOPSwitch Chosen SP, ISRMS, IRIPPLE DIAS, ODS24. Calculate PIVS, PIVBN P YNYNY £ BM£ 300018. Calculate Lg19. Lg � 0.051 mm20. Calculate OD, DIA, CMA21. 200 £ CMA £ 500 effectivenessÓ. Using smaller components will usually lead toa less expensive power supply. However, for applications with A Step 25-35 Select Other Components From Step 24 NY 27. Select Output Capacitor28. Switching Ripple Too High29. Select Output Post Filter L, C30. Select Bias Rectifier31. Select Bias Capacitor & Series Resistor33. Select Feedback Circuit Compenents According to Reference Designs: RD1, ST202A, ST204A34. Select Bridge Rectifier35. Design Complete PI-1870-052896 flyback power supply design, and automates most calculations. Designers therefore are relieved from thetedious calculations involved in the complicated and highly iterative design process. Anytime a parameter is involved in a calculation,example (A1) denotes column A and row 1. Note that all user provided inputs are in column B and all spreadsheet calculated resultsare in column D. Column C is reserved for intermediate variables needed in some complicated calculations. Look up tables and rulesof thumb are also provided wherever appropriate, to facilitate the design task. For questions regarding any particular step of this, per Table 1(B3), per Table 1(B4): 50Hz or 60Hz(B5): 100KHz(B6): in Volts(B7): in Watts(B8): 0.8 if no better reference data available(B9)¥ Loss allocation factor, Z: 0.5 if no better reference data available(B10), per Table 2(B11) FeedbackOutput LoadLineReferenceCircuitVAccuracy RegulationRegulationDesignPrimary/basic 5.710% 1.5%RD15% 1.5%RD1Opto/Zener125% 0.5%ST202AOpto/TL431121% 0.2%ST204A Table 2 A = 3 mS(B12), per Table 3(B13) based on input voltages per Table 4(B16) = 10 V(B17) = 0.4 for 100/115 VAC or universal input(B20) 0.6 for 230 VAC Table 3VMIN (V)³³90³Input (VAC)100/115CIN (mF/Watt of PO)Input (VAC)100/115 Table 4 Minimum(Most Continuous) Table 5Input (VAC)100/115Universal MaximumKV(V)60VCLO (V)90 AVG : in Amps(D38): in Amps(D39): in Amps(D40)RMS : in Amps(D41) of the selected against required peak current I until K = 1.0 orusing AN-18 Appendix A, Table 2 and determine A: in cm(B25)Bobbin width, BW : in mm(B27) 2.0 throughout iteration)(B29)= 1 turn/volt for 100/115 VAC(B30) A ¥ Set safety margin, M. Use 3 mm (118 mils) for margin wound(B28) 2000; in Gauss(D48) 0.051 mm(D51) 200;(D58)¥ Primary minimum conductor diameter, DIA: in mm(D55)¥ Primary maximum wire outside diameter, OD: in mm(D53)SP, S, SP : in Amps(D61): in Amps(D62)RIPPLE : in Amps(D64) : in mm(D68) : in mm(D69): in Volts(D74): in Volts(D75) (from Step 4): Notes: 1. P6KE91:91V/5W; Motorola P6KE200:200V/5W; Motorola BYV26B:400V/1A, UFR; Philips BYV26C:600V/1A, UFR; PhilipsInput (VAC)V(V)ZenerDiode100/11590P6KE91BYV26BUniversal200P6KE200BYV26C230200P6KE200BYV26C Table 7 BLgL­­NSCore Table 6 ¥ Capacitor ripple current specified @ 105 is from Step 23. OutputOutput Capacitor 5V to 24V, 1A330uF, 35V, low ESR, electrolytic 5V to 24V, 2A1000uF, 35V, low ESR, electrolyticRectifier DiodeV (V)I(A)ManufacturerSchottky 1N5819401.0Motorola 1N5822403.0Motorola MBR745457.5Motorola MBR10454510Motorola MBR16454516MotorolaUFR UF40021001.0GI MUR1101001.0Motorola MUR1202001.0Motorola UF40032001.0GI BYV27-2002002.0Philips, GI UF54011003.0GI UF54022003.0GI MUR4101004.0Motorola MUR4202004.0Motorola MUR8101008.0Motorola MUR8202008.0Motorola BYW29-2002008.0Philips, GI BYV32-20020020Philips A Step 28. to Step 29.Add output LC post filter if and only if output switching ripple voltage is not within specification:¥ Inductor L: 2.2 to 4.7H. Use ferrite bead for low current ( 1A) output and standard off the shelf choke for higher current¥ Capacitor, C:120uF, 35V, low ESR electrolytic 1.25 x PIV is from Step 24 and V is the rated reverse VPF is from step 1 and PF is the power factorRectifierV(V)Manufacturer1N414875MotorolaBAV21200PhilipsUF4003200GI Table 9 In-depth Information and V for most commonlyuniversal input. A cases. Applications with a different input voltage range can be is the ratio of output power to input power. Sincerepresentative of similar power supplies. Switching powerhigher voltage outputs (12V and above). If this data is not and an efficiency x (1- watts of power is lost somewhere in the system:considered in the transformer design. Note that the powerdelivered to the clamp circuit. The ratio of the secondary lossStep 2.Decide on a Feedback/sense circuit and biasFour types of feedback/sense circuits are recommended. The� 5V). Outputaccuracy can be improved for the primary feedback circuit byadding a 22V Zener and a capacitor as shown in Figure 4. The +5VRTN 10 nF 400 VC5 47 mF 10 VD2 1N5822D3 1N4148C2 330 mF 10 VT1D1 C3 100 mF 10 V 15 WVR1 3.3 mH -U1 SS 210 13458DC INPUT TRD1 A Figure 4. RD1 Reference Design Board (Enhanced).Figure 5. ST202A Reference Design Board. +5VRTN 10nF 400 VC5 47 mF 10 VC4 100 nF 50 VD2 1N5822D3 BAV21C2 330 mF 10 VT1D1 C3 100 mF 10 V 15 WVR1 3.3 mH SS210 1N5251D 22 V 1% 213458 -DC INPUTTRD1-1 PI-1852-050696 7.5 VRTN 47mFD2 UG8BTD3 1N4148R2 68 WVR2 1N5234B 6.2 VC3 120 mF 25 VT1D1 680 mF 25 V 400 VC1 33 mF 400 V 39 WU2 NEC2501 TOP202YAI SOURCECONTROL C4 0.1 mF 1 nF Y1 3.3 mH F1 3.15 AJ1C6 0.1 mFL2 22 mHL N 13 15 VRTN 400 VC1 47 mF 400 VC5 47 mFC4 0.1 mFU1 TOP204YAIR3 6.2 WR2 200 W 1/2 WD2 MUR610CTD3 1N4148C2 1000 mF 35 VT1D1 C7 1 nF Y1 SOURCECONTROL C3 120 mF 25 V U2 NEC2501U3 TL431R4 49.9 kWR5 10 kW C9 0.1 mFR1 510 WVR1 3.3 mH F1 3.15 AJ1C6 0.1 mFL2 33 mHL N or lowerripple, whereas lower values of C result in significantly lower increasing cost due to increased peak operatingcurrent demand. Lower values of C also increase input ripple (or vice versa)equation with no closed form solution. The equation shown MINACMIN=´- is typically 3 ms, and can be verified by direct measurement.Step 4.Determine reflected output voltage V andpower and voltage ranges. An intermediate solution is to use anopto-coupler with a Zener sense circuit (Figure 5). ThisStep 3.Determine input capacitor C and minimum (Figure 1), the resulting High Voltage DC bus(V+) has a ripple voltage as shown in Figure 7. The minimuman important parameter for the design of the power supply. AF/Watt for 230VAC. This results in a Vrespectively. The C value obtained by using this rule represents increase capacitor cost without A low current values and at room temperature. High voltagequite resistive. Consequently, the clamp voltage at high current can be much higher. Experimental can be as high as 40% above theCLMCLOclamp Zener. In addition, it is important to allow an additionalVVVVDRAINMAXOR=+´´+(..)141520 consistent with the breakdown voltage ratingafter taking into account all of the above effects. As will be seen is shown in Figure1. When the is off and the secondary is conducting,the transformer by the turns ratio. This reflected voltage V drain node.input voltage is at its maximum value. The maximum DC input MAXACMAX the drain also sees a large voltage spikeinductance of the primary winding (see Figures 8 and 9). Toacross the primary winding. A Zener clamp as shown instart up transients. The nominal value of Zener clamp voltage needs to be 50% (determined empirically) greater than theprimary to the secondary. Experimental measurements showbe quickly established through the leakage inductance. Lower tC PO = Output Power L = Line Frequency (50 or 60Hz) C = Conduction Angle Use 3ms if unknown h = Efficiency - Assume 0.8 if unknown VACMINMIN´2 MINACMIN=´-()( V+Figure 7. Input Voltage Waveform. 15Figure 8. Reflected Voltage (VOR) and Clamp Zener Voltage (VCLO) - 100/115 VAC Input. DSSVOR = 60 V MARGIN = 17 V 350 V313 V333 V277 V247 V187 V0 V0 VD @ 24%VCLO = 1.5 x VOR = 90V CLM = 1.4 x VCLO =126VVCLM VCLOVMAX For 100/115 VAC Input Using 350 V TOPSwitch Use VOR = 60 V and 90 V Zener ClampPI-1855-050696OR) and Clamp Zener Voltage (VCLO) - Universal/230 VAC Input. TOPSwitch Use VOR = 135 V and 200 V Zener ClampPI-1856-050696 DSSVOR = 135 V MARGIN = 25 V 700 V655V675 V575 V510 V375 V0 V0 VD @ 26%VCLO = 1.5 x VOR = 200V CLM = 1.4 x VCLO = 280VVCLM VCLOVMAX A will result in a larger D which reduces operating current for the same output power. If comes close to the maximum allowable duty cycle of the (64%) then V should not be increased any further. based on =´=2132187 of 187V using a 350V results in a standard of 60V and a margin of17V. Likewise in 230VAC or Universal application, a V of 375V. At this value of will allow for a standard Zener value of 135V leaving a margin of25V (see Figure 9). If these margins seem too small, it is breakdown voltage increases at highStep 5.Determine maximum duty cycle at low line and V are known, it is easy to calculate the VVVORMINDS is the average Drain to Source voltage during ON time. As shown in Figures 10 and 11, with V set to zero, ranges from 36%/40% for single input voltageapplications to 60% for the universal input application. In should be set to approximately 10V which results in directly increases the output power capability of a allows larger V and. Therefore, a narrower input voltage range DSSVMINVOR = 60 V 350 V (700 V)216 V (520 V)236 V (540 V)180 V (440 V)150 V (375 V)90 V (240 V)0 V0 VDMAX @ 40% VCLM VCLOVCLM = 1.4 x VCLO =126V BLOCKING DIODE FORWARD RECOVERY = 20 V (135 V)(36%) PI-1857-050696 (200 V)Figure 10. Determine DMAX - 100/115 VAC (230 VAC) Input 17 BVDSSVMINVOR = 135 V 700 V370 V390 V290 V225 V90 V0 V0 VDMAX @ 60% BLOCKING DIODE FORWARD RECOVERY = 20 V VCLM VCLO Step 6.Set ripple current I to peak current I ratio K ¥Starting with K = 0.4 for 100/115 VAC or universal inputRP the loop independent of operating mode. Setting K to the valuesrecommended above allows continuous mode operation at low for the application. of 0.6 is recommended for 230VAC (compared to 0.4 forStep 7.Determine primary waveform parameters I at low line is simply the input and D already determined, the shape of the current and A IIKRPRP IIDRMSPMAX=´´-+Step 8.Select based on data specification and required ILIMITP in datasheet is specified at room temperature. To accommodate thetemperature limit should be derated by 10%. This can be in the datasheet. The smallest higher than this value should be selected as theStep 9 to Step 10. Check thermal limitation - Use if necessary to reduce power loss¥Calculate PIRCIRRMSDSON=´°¥Calculate PCVVfCXTXTMAXORS@´´+´¥Calculate junction temperature Tj of TCPPJIRCXTJA=°++´25()¥�If Tj 100¥For non-critical applications, refer to AN-14 Table 2 thermal environment can vary significantly fromapplication to application. Fully enclosed lap top adapters withsurface temperatures on the outside of the box. Heat sinks insurface of the box. The actual power capability at a giventhe box. In contrast, a PC power supply has a fan whichprovides forced air cooling. Here a larger heat sink could be the to see whether it is acceptable in a given application. and the RDS(ON) is present, the switching losses (Palso be estimated. Even though low line is usually the worst case losses, it is prudent to verify this by calculating the is known, the IPIR IP }IR}KRP = IR IP KRP = 1.0DRAIN CURRENT WAVEFORM SHAPESContinuous Mode (a)Discontinuous Mode (b) (specified in the datasheet), and from (usually specified in the heat sink datasheet). If a package without a heatsink tab is used, such as an8 pin DIP, then a typical die to ambient thermal impedance, ¯calculations. It is recommended that the die temperature be keptStep 11. Check minimum I of the selected against required I. Increase K. However, if so desired, a trade-off and core size can be accomplished by value. Larger K allows the use of a smaller implies. This is very important when the best suited that can be chosen for a designstill ends up with significant extra current capability. It is then. In addition to affecting the size of the also influences supply efficiency. Larger results in higher primary RMS current I and higher conduction loss while lower K results in lower and lower loss. For applications with tight value can offer the optimum solution once is first chosen, the flexibility iscertainly available for other design options. Experienced value based x I x (I - I. The primary inductance L can be PRP´´-´-+ is the efficiency and Z is the loss allocation factor. If Z=1, alllosses are on the secondary side. If Z = 0, all losses are on theprimary side. Z is simply the ratio of secondary loss to total loss. If nobased on AN-18, Appendix A, Table 2 and determinetypes for various power ranges. Notice that there are twocore and bobbin for a given output power. Margin winding,will require wider bobbins and therefore, longer/taller cores. Ifwith the smallest EE type core for the power level. EE cores areusually the least expensive type. The two digit number followingthe core type indicates the core size in mm. For 100KHzTDK PC40 material is a good first choice. Other ferritemanufacturers. Lower frequency core materials such as Philips and bobbinStep 14. Set number of primary layers L and numberStep 15. Calculate number of primary turns N andStep 16 to Step 22. Check B, core/bobbin until withinIn addition to the selection of core and bobbin, a total of nine and bias N. Because the bias winding, the above parameters are all interdependent. AUsing 1 turn/volt for 100/115 VAC and 0.6 turn/volt for 230 VAC A or universal inputs is a good assumption. As an example, for a of 15V plus the of 0.7V, a 16 turn secondary wouldbe used as the initial value. The primary number of turns N is by the ratio is the reflected output voltage, V is the output can be derived BDB is the bias voltage and V is the bias rectifier forward BWLBWM=´-´´()2The closest standard magnet wire gauge that is less than or equalto this diameter can be selected. Determine the bare conductordiameter DIA of this wire gauge using information from a wiretable. The next step is to find out if this conductor size is. The current capacity for 127254Note that in the AN-17 spreadsheet, DIA is actually derivedfrom OD using an empirical equation. A practical wire size, must be increased to bring it within the is less than required to generate with number of primary turns N must also be =´´´ and ungapped effective can be found from the data sheets for the core. Lmanufacturability. If L is less than 51 process in itself. When N is changed, N and N will changeaccording to ratios already established. Similarly, any change and L to make Step 23. DetermineSP, S, can be derived from the primary and the turns ratio between primary and secondary SPP of the secondary is always identical to that of thecurrent with duty cycle (1-D). Therefore, the secondary RMS can be expressed in a manner similar to the primary IIDSRMSSPMAX=´-´-+ is the RMS ripple current of the output capacitor. Because IIISRMSO is the power supply output current which can be calculated, available, the minimum CMAI127254 using an empirical equation.to provide the same effective cross sectional area. The parallel. For turns of two parallel strands of by twice thethickness of the insulator. Therefore, the maximum outside BWM and an insulated outsideStep 24. Determine maximum peak inverse voltages PIVVVSOMAX=+´ PIVVVBBMAX=+´Step 25. Select clamp Zener and blocking diode for iscalculated in Step 24. The diodes should be chosen with a equal to or greater than 1.25 X PIV A selection. Capacitor ESR directly determines the output ripplecapacitor case size. Consider two Nichicon PL series capacitors:F/35V. Both capacitors have a case size. To keep control loop bandwidth high, the IIIRIPPLESRMSO is the secondary winding RMS current and I is theStep 28 to Step 29. Select Output post filter L, Cthe bias output, a 0.1 uF, 50V ceramic capacitor always meetsStep 32. Select Control pin capacitor and series takesconfigurations. Low ESR capacitors should not be used for this typical) improves the loop stability by introducing a zero. resistor in series with this capacitor is value of less than one (continuous¥Primary feedback: Refer to RD1¥Opto/Zener feedback: Refer to ST202A¥Opto/TL431: Refer to ST204A¥Select opto-coupler with CTR between 50% and 200%Step 34. Select bridge rectifier based on input voltage VPF 2 x I is the rated RMS current of the 1.25 x 1.414 x V; where V is the rated reverse flyback converter. Once built, the power ¥Constant current/power output: DN-14¥PC board layout: AN-14¥Transformer design: AN-17¥Transformer construction: AN-18¥Efficiency: AN-19¥EMI and safety: AN-15¥Transient: AN-20and/or constant power outputs (DN-14), input under voltage flyback. AN-18 A VIN TOPSwitch DRAINSOURCECONTROL D2C1RL SNP power integrated circuit. TOPSwitch issupplies. Designing the power supply is greatly simplifiedbecause few external components are required. The highswitching frequency of 100 KHz reduces the size of the power was designed for use in isolated power suppliesor DC to DC converters. Power levels up to 50 Watts can bea 195 to 265 VAC input range. Operation from lower inputThe flyback power supply is described in detail. Ideal and non-ideal circuit operation is explained. The difference between theThe benefits of high frequency operation are presented. Othertypes of power supplies using both linear and switchingoff-line, isolated, power supply applications. The flybackrequires a power transformer. Most switching power supplieswidth modulated switching waveform into a DC output. Thestorage, isolation, and voltage transformation. As compared toresulting in the lowest cost. The flyback topology retains theseup to 10 amperes. Component stress levels above 100 watts ortransformer. This means that secondary side regulation can beprimary and secondary circuitry. Single or multiple, higher orComparison to Other TechniquesThese are briefly examined below. Additional information canlinear regulator as shown in Figure 2. This type of power supply available. The buck, boost, and forward converters are describedbelow. Multiswitch and resonant converters are also briefly - The buck converter, shown in Figure 3, is - The boost converter, shown in Figure 4, is - The forward converter, shown in Figure5, is an isolated version of the Buck. Single or multiple, positivetransformer design. This topology can be useful for output - Multiple switch convertertransistor flyback, and two transistor forward converters. Allare much more complex and costly. They are used to implement - Resonantby conventional switching power supplies. Quasi resonantwaveform. In general, resonant and quasi-resonant convertersquasi-square wave VINRL WITH ISOLATION PI-1735-021296 REGULATOR60 Hz TRANSFORMER AC INVO Figure 5. Forward Converter Circuit. VINVORL Figure 3. Buck Converter Circuit. VINVORL Figure 4. Boost Converter Circuit. A switching power supply. Peak voltage or current stress levelstopology is used. The most effective resonant converters usecomplexity. Resonant converters are not cost effective at low isshown in Figure 1. Transformer T1 is used both for energy is on, secondary diode D2 is reverse VVtPRIIINDSONON is the primary current in amperes, I is the initial value of the is the DC input voltage after the is the drain to source voltage drop across the is the on time of the is the transformer primary inductance in Henries. Since from the output turns off, the magnetic flux in thewinding is reversed. D2 turns on, and the energy stored in the is dischargedinto the load circuit, supplying current to the load R andreplenishing the charge depleted from C1 during the on time. turns off will be equal to I x N on time and N is theturns. The secondary current decays from its initial value VVtNODOFFP+´´ is the output voltage of the supply, V is the forward voltage is the off time. If the secondary at the end of the offtime. If I decays to zero at or before the end of the off time, the supply is running in the discontinuous mode. If Iis on. Current I ramps up linearly in the transformer primary PI-1616-021496 IND2 C1 RLVO+-+- IISEC VINVDRAIN1Interval IIISECVIN+VOR DS(ON) DRAINSOURCECONTROL PVOR Figure 6. Ideal Flyback Converter Waveforms - Discontinuous Mode. core. The drain to source voltage V across isnearly zero during this interval. The output diode preventspolarity. Since the transformer secondary is isolated from theturns off. The energy stored in the magnetic field of thesecondary windings to reverse polarity. In an ideal circuit the instantly stops flowing while the secondary instantly starts flowing (it will be shown later howimportant it is to consider non-ideal behavior). The voltagevoltage and diode forward voltage. The secondary voltage isprimary winding. Note that the drain to source voltage across during this interval of operation is equal to the and the input voltage. This reflected voltage must be taken into account when. The reflected voltage can also be used to = 0). No currentdefines the discontinuous mode of operation). Note that the has decayed to thelevel of the input voltage. Since the stored energy of the ELI=´´´ PLIfOPPS=´´´´ is the operating frequency of the power supply, and is the efficiency. Substituting the expression of Equation (1) for (with I = 0 and V = 0), and defining t as D/f is the operating frequency. controller will adjust the duty cycle of the primary switch tovoltage. The duty cycle is a function of both the input voltagecontinuous mode of operation. The reference circuit is the sameThe secondary current Ias in the discontinuous mode, so that the third interval ofoperation (3) does not exist. The primary current I starts with reflected back through the transformer turns ratio. The at the instant of turnas previously discussed. The reflected output voltage state turns PI-1736-021496 VINVDRAINIPRIISECVIN+VOR Interval12 A time. This means that ()()VVDVVDINDSON+´- VVVOINDSON=-´ off time determine continuous ordiscontinuous operation. This dependence is shown inEquation (2). The boundary of continuous versus discontinuous INOINO´´´´ is the output current at the boundary betweencycle is exactly equal to the integral of the transformer secondaryoutput current over the off time period. This means that duringIf the output current is greater than the right hand side ofmode. A smaller transformer primary inductance will give upin discontinuous conduction mode. Conversely, a larger primarycycle and operate in continuous mode. If the load current ismode. Also, if the input voltage is increased for a given load,associated waveforms for the discontinuous and continuousoperating modes are shown in Figures 8 and 9. The non-idealinductors and one capacitor. The inductor L is the leakage is the leakage inductance of the secondary INLKP RLVO+-+- IISEC VINVDRAIN Leakage Spike Voltage 1Interval VPIISECSlope = di/dt VIN+VOR 0 DRAINSOURCECONTROL D2 DSC1LKS CDRAIN = COSS+CXT winding on the power transformer. The capacitor C and C which are the output capacitanceand the transformer winding capacitance, respectively. Theseintervals of operation per switching cycle (see Figure 8). The turns on, discharging C. The energy stored by these capacitances at the end of at the beginningof the turn on interval. This dissipated energy is proportional tothe square of the voltage on the parasitic capacitances. Becausehigh input voltage. Leakage inductance has little effect during turns off. Theprevious interval is now transferred to the secondary circuit. A and L are both trying to oppose changes in current flow. is trying to maintain primary current flow, and L is tryingto block secondary current flow. There is a Òcrossover regionÓcurrent ramps up. The primary current ramps down to zero withcircuit voltage levels. The secondary current ramps up to theinductance and circuit voltage levels. The big problem is thatinterval. The decaying primary current ends up flowing into and C which charge up to a peak voltage V. This peakÒleakage spikeÓ. In a practical flyback supply, thethe energy stored during the first interval. The drain and input voltage Valone. Thiscapacitance and the primary inductance to create a decaying turnson again. This waveform ÒmodulatesÓ the voltage on (and the and C turns on at the beginning of theare present as in the discontinuous mode. In addition, the non-important. An ideal rectifier has no forward voltage drop, andswitches infinitely fast. An actual diode has a finite forwardvoltage drop, and takes a finite time to switch off. A PN junctionreverse bias and switch to the off state. In the case of a Schottkycurrent spike that persists until the diode switches off. This during its turn ontransition. The amplitude and duration of this current spike isdependent on the speed of the diode. For 100 KHz powersupplies, ultrafast diodes (trr ) Non-ideal operating waveforms of a continuous mode flybackconverter are shown in Figure 9. During the interval (1) of turns on while current is still flowing inthe transformer secondary. This means that the drain voltage atturns ratio. This results in higher turn-on powercircuit. In addition, the current in the secondary leakagebe turned off. This results in a turn on current crossover while Interval PI-1618-021496 VINVDRAIN Leakage Spike Voltage 1Interval 2VPIPRIISECSlope = di/dt VIN+VOR 0 D1 Reverse Recovery Current Spike Mode. A ramps up. Once the secondary leakage inductance is discharged,of the primary current. This can result in spurious operation ofa current limit protection circuit. The provides turns off, operation in the continuous modeis similar to that of the discontinuous mode. The primary andeffects of the transformer leakage inductance. This gives rise tomode. The drain to source voltage rises to the sumback through the transformer turns ratio. Unlike the turns on again, so that there is no interval (3) where2. Ralph E. Tarter, Solid State Power Conversion Handbook,3. Abraham I. Pressman, Switching Power Supply Design (2nd4. Application Information 472, C. van Velthooven, Properties5. Col. William McLyman, Transformer and Inductor Design6. Col. William McLyman, Magnetic Core Selection for7. Philips Components, Ferroxcube Magnetic Design Manual,8.Ferdinand C. Geerlings, ÒSMPS Power Inductor and9.Ferdinand C. Geerlings, ÒSMPS Power Inductor Design and10. Philips Semiconductors, Power Semiconductor11. Technical Information 042, Using very fast recovery diodeson SMPS, Philips Components, 1978 (Ordering Code 939912. Brian Huffman, ÒBuild Reliable Power Supplies by Limiting13. Jon Schleisner, ÒSelecting the Optimum Voltage Transient 31 A Phone:81¥(0)¥45¥471¥1021Fax:81¥(0)¥45¥471¥3717Phone:408¥523¥9265Fax:408¥523¥9365Main:408¥523¥9200Phone:408¥523¥9265Fax:408¥523¥9365 Phone:408¥523¥9265Fax:408¥523¥9365 are registered trademarks of Power Integrations, Inc.World Wide408¥523¥9260Americas408¥523¥9361Japan81¥(0)¥45¥471¥3717Asia/Oceania408¥523¥9364Phone:44¥(0)¥1753¥622¥208Fax:44¥(0)¥1753¥622¥209 AN-16 A6/96 Phone:81¥(0)¥45¥471¥1021Fax:81¥(0)¥45¥471¥3717Phone:408¥523¥9265Fax:408¥523¥9365Main:408¥523¥9200Phone:408¥523¥9265Fax:408¥523¥9365 Phone:408¥523¥9265Fax:408¥523¥9365World Wide408¥523¥9260Americas408¥523¥9361Japan81¥(0)¥45¥471¥3717Asia/Oceania408¥523¥9364Phone:44¥(0)¥1753¥622¥208Fax:44¥(0)¥1753¥622¥209 A6/96 AN-1631 AN-16 A6/96 8.Ferdinand C. Geerlings, ÒSMPS Power Inductor and9.Ferdinand C. Geerlings, ÒSMPS Power Inductor Design andon SMPS, Philips Components, 1978 (Ordering Code 9399 A6/96 AN-1629winding on the power transformer. The capacitor CDRAIN is thesum of COSS and CXT which are the TOPSwitch output capacitanceand the transformer winding capacitance, respectively. Theseparasitic circuit elements are present in any real-life flybackAs previously shown, the discontinuous mode circuit has threeintervals of operation per switching cycle (see Figure 8). TheIn the first interval (1) the TOPSwitch turns on, discharging COSSand CXT. The energy stored by these capacitances at the end ofthe previous cycle is dissipated in the TOPSwitch at the beginningof the turn on interval. This dissipated energy is proportional tothe square of the voltage on the parasitic capacitances. BecauseIn interval (2) of operation, the TOPSwitch turns off. Theenergy stored in the transformer magnetic field during theprevious interval is now transferred to the secondary circuit. AKP and LKS are both trying to oppose changes in current flow.LKP is trying to maintain primary current flow, and LKS is tryingto block secondary current flow. There is a Òcrossover regionÓinterval. The decaying primary current ends up flowing intoOSS and CXT which charge up to a peak voltage VP. This peakvoltage, caused by leakage inductance, will be referred to as theTOPSwitch flyback supply, theleakage spike should be clamped to a value below the TOPSwitchbreakdown voltage rating.During interval (3) of operation, the reflected output voltagegoes to zero. The transformer magnetic field has given up allTOPSwitch drainto source voltage makes a transition from the level equal to theOR and input voltage VINdown to a level equal to the input voltage VIN alone. Thistransition excites the resonant tank circuit formed by the strayTOPSwitch turnson again. This waveform ÒmodulatesÓ the voltage on (and theOSS and CXT, determining thepower loss when TOPSwitch turns on at the beginning of thenext cycle.In the continuous mode of operation, the same parasitic elementsare present as in the discontinuous mode. In addition, the non-rr) due to the fact thatthe minority charge carriers must be swept from the junction byrr) is associated with a reverse recoverycurrent spike that persists until the diode switches off. ThisTOPSwitch during its turn ontransition. The amplitude and duration of this current spike is Non-ideal operating waveforms of a continuous mode flybackconverter are shown in Figure 9. During the interval (1) ofTOPSwitch turns on while current is still flowing inthe transformer secondary. This means that the drain voltage atTOPSwitch turn-on powerdissipation than in the discontinuous mode, due to the extra Crossover\rInterval PI-1618-021496 VINVDRAIN Leakage\rSpike\rVoltage 1Interval\r\r2VPIPRIISECSlope = di/dt VIN+VOR 0 D1\rReverse\rRecovery\rCurrent\rSpike Figure 9. Non-ideal Flyback Converter Waveforms - ContinuousMode. AN-16 A6/96 28time. This means that ()()VVDVVDINDSON+´- VVVOINDSON=-´ INOINO´´´´ PI-1617-021496 VINLKP \rRLVO+-+-+- IPRIISEC VINVDRAIN Leakage\rSpike\rVoltage 1Interval\r\r23VPIPRIISECSlope = di/dt VIN+VOR 0 DRAINSOURCECONTROL D2\r VDSC1LKS CDRAIN =\rCOSS+CXT Figure 8. Non-ideal Flyback Converter Waveforms - Discontinuous Mode. A6/96 AN-1627core. The drain to source voltage VDS(ON) across TOPSwitch isnearly zero during this interval. The output diode preventscurrent flow in the secondary due to the transformer dotThe second interval (2) of operation starts when TOPSwitchturns off. The energy stored in the magnetic field of thetransformer causes the voltage across both the primary andPRI instantly stops flowing while the secondarycurrent ISEC instantly starts flowing (it will be shown later howimportant it is to consider non-ideal behavior). The voltageTOPSwitch during this interval of operation is equal to thesum of the reflected output voltage VOR and the input voltageVIN. This reflected voltage must be taken into account whenselecting the transformer turns ratio to avoid excessive voltageTOPSwitch. The reflected voltage can also be used toindirectly sense the output voltage of the supply from theThe energy stored in the primary inductance of the transformerduring the first interval of operation supplies current to the loadThe third interval (3) of operation occurs when the magneticfield within the core has decayed to zero (ISEC = 0). No currentflows in the primary or secondary of the transformer (whichTOPSwitch has decayed to thelevel of the input voltage. Since the stored energy of theThe energy delivered to the load each cycle by the transformeris given by ELI=´´´ PLIfOPPS=´´´´ The secondary current Ioperation (3) does not exist. The primary current I reflected back through the transformer turns ratio. The 0 PI-1736-021496 VINVDRAINIPRIISECVIN+VOR 12 AN-16 A6/96 26switching power supply. Peak voltage or current stress levelsare higher than quasi square wave power converters, dependingFlyback TheoryBasic Flyback OperationA basic flyback power supply circuit utilizing TOPSwitch isshown in Figure 1. Transformer T1 is used both for energystorage, output isolation, and output voltage transformation.TOPSwitch is on, secondary diode D2 is reversebiased, and current ramps up in the transformer primary winding VVtPRIIINDSONONreplenishing the charge depleted from C1 during the on time. VVtNODOFFP+´´ is the decays to zero at or before the end of the 0 PI-1616-021496 VIND2\r C1\rRLVO+-+-+- IPRIISEC VINVDRAIN1Interval\r\r23IIPRIISECVIN+VOR VDS(ON) DRAINSOURCECONTROL\r PVOR Figure 6. Ideal Flyback Converter Waveforms - Discontinuous Mode. A6/96 quasi-square wave PI-1720-120595 VINRL CONTROL FEEDBACKWITH ISOLATION PI-1735-021296 LINEAR\rREGULATOR60 Hz\rTRANSFORMER AC\rINVO Figure 2. Linear Regulator Circuit.Figure 5. Forward Converter Circuit. PI-1788-021296 CONTROL FEEDBACK VINVORL Figure 3. Buck Converter Circuit. PI-1789-021296 CONTROL FEEDBACK VINVORL Figure 4. Boost Converter Circuit. AN-16 A6/96 24 PI-1615-021296 FEEDBACK VIN TOPSwitch DRAINSOURCECONTROL T1D2C1RL NSNP isComparison to Other Techniques A6/96 ¥Constant current/power output: DN-14¥PC board layout: AN-14¥Transformer design: AN-17¥Transformer construction: AN-18¥Efficiency: AN-19¥EMI and safety: AN-15¥Transient: AN-20and/or constant power outputs (DN-14), input under voltage AN-16 A6/96 22Step 27. Select Output capacitorESR is the most important parameter for output filter capacitorselection. Capacitor ESR directly determines the output ripplemF/6.3V and 390mF/35V. Both capacitors have a case sizeof 10 mm diameter and 25 mm length, and both have the sameW. To keep control loop bandwidth high, thesmaller capacitance, higher voltage rating capacitor is preferred.Ripple current is typically specified at 105oC ambient which ismuch higher than the ambient temperature required in mostapplications. Therefore, it is possible to operate the capacitor atActual ripple current of the output capacitor can be calculatedas follows: IIIRIPPLESRMSOStep 28 to Step 29. Select Output post filter L, C¥Primary feedback: Refer to RD1¥Opto/Zener feedback: Refer to ST202A¥Opto/TL431: Refer to ST204A¥Select opto-coupler with CTR between 50% and 200% VPF A6/96 SP, S, SPP IIDSRMSSP=´-´-+ IIISRMSO IPVOOO=With the secondary RMS current ISRMS available, the minimumsecondary wire diameter DIAS (in mm), can be calculated asfollows: CMAI127254 BWM PIVVVSOMAX=+´ PIVVVBBMAX=+´ AN-16 A6/96 20or universal inputs is a good assumption. As an example, for a115VAC input and an output voltage VO of 15V plus therectifier forward drop VD of 0.7V, a 16 turn secondary wouldbe used as the initial value. The primary number of turns NP isrelated to the secondary number of turns NS by the ratiobetween VOR and VO + VD NNVVVPSOROD=´+where VOR is the reflected output voltage, VO is the outputvoltage and VD is the output rectifier forward voltage drop.Similarly, the number of bias winding turns NB can be derivedfrom BDB BWLBWM=´-´ 127254Note that in the AN-17 spreadsheet, DIA is actually derived BILNAMPPPe=´´´100Ae is the effective cross sectional area of the core.If BM is greater than 3000 Gauss, either the core cross sectionalarea (core size) or NP must be increased to bring it within the2000 to 3000 range. On the other hand, if BM is less than2000 Gauss, a smaller core or fewer turns on the primary can beIn addition to BM, the core gap length Lg required to generateinductance LP with number of primary turns NP must also bechecked: =´´´ ALNLGPP=´10002As can be seen, the transformer design is a highly iterativeP is changed, NS and NB will changeaccording to ratios already established. Similarly, any changeM and Lg to makesure that they are within the specified limits. A6/96 . Increase K PRP´´-´-+based on AN-18, Appendix A, Table 2 and determineStep 16 to Step 22. Check B, core/bobbin until withinUsing 1 turn/volt for 100/115 VAC and 0.6 turn/volt for 230 VAC AN-16 A6/96 18 IIKRPRP IIDRMSPMAX=´´-+Step 8.Select 09.LIMITP¥Calculate PIRCIRRMSDSON=´°¥Calculate PCVVfXTMAXORS@´´+´¥Calculate junction temperature Tj of TCPPIRCXTJA=°++´25()¥�If Tj 100¥For non-critical applications, refer to AN-14 Table 2 thermal environment can vary significantly fromDS(ON) PI-1902-61096 IPIR\r\r IP }IR}KRP = IR\r\r\rIP\r\r KRP = 1.0DRAIN CURRENT WAVEFORM SHAPESContinuous Mode\r(a)Discontinuous Mode\r(b)Figure 12. Primary Current Waveform. A6/96 AN-1617 BVDSSVMINVOR = 135 V\r\r700 V370 V390 V290 V225 V90 V0 V0 VDMAX @ 60% BLOCKING DIODE FORWARD RECOVERY = 20 V VCLM VCLO Step 6.Set ripple current I ¥Starting with KRP recommended above allows continuous mode operation at low for the application.Step 7.Determine primary waveform parameters I IPVAVGOMIN=´hWith KRP and DMAX already determined, the shape of the currentwaveform is known. Due to the simple geometry of thewaveform, the Primary peak current IP, ripple current IR andRMS current IRMS can be easily derived as a function of IAVG: AN-16 A6/96 16later, a higher VOR will result in a larger DMAX which reducesTOPSwitch operating current for the same output power. IfDMAX comes close to the maximum allowable duty cycle of theTOPSwitch (64%) then VOR should not be increased any further.For a 100/115 VAC power supply the VACMAX based on115 VAC would be 132 VAC which corresponds to: =´=2132187Step 5.Determine maximum duty cycle at low line VVVORMINDS BVDSSVMINVOR = 60 V\r\r350 V (700 V)216 V (520 V)236 V (540 V)180 V (440 V)150 V (375 V)90 V (240 V)0 V0 VDMAX @ 40% VCLM VCLOVCLM = 1.4 x VCLO =126V BLOCKING DIODE FORWARD RECOVERY = 20 V (135 V)(36%) PI-1857-050696 (200 V)Figure 10. Determine DMAX - 100/115 VAC (230 VAC) Input A6/96 AN-1615Figure 8. Reflected Voltage (VOR) and Clamp Zener Voltage (VCLO) - 100/115 VAC Input. BVDSSVOR = 60 V\r\rMARGIN = 17 V BLOCKING DIODE FORWARD RECOVERY = 20 V350 V313 V333 V277 V247 V187 V0 V0 VD @ 24%VCLO = 1.5 x VOR = 90V \r\rVCLM = 1.4 x VCLO =126VVCLM VCLOVMAX For 100/115 VAC Input Using 350 V TOPSwitch\rUse VOR = 60 V and 90 V Zener ClampPI-1855-050696Figure 9. Reflected Voltage (VOR) and Clamp Zener Voltage (VCLO) - Universal/230 VAC Input. For Universal/230 VAC Input Using 700 V TOPSwitch\rUse VOR = 135 V and 200 V Zener ClampPI-1856-050696 BVDSSVOR = 135 V\r\rMARGIN = 25 V BLOCKING DIODE FORWARD RECOVERY = 20 V700 V655V675 V575 V510 V375 V0 V0 VD @ 26%VCLO = 1.5 x VOR = 200V \r\rVCLM = 1.4 x VCLO = 280VVCLM VCLOVMAX AN-16 A6/96 14.VVVVDRAINMAX=+´´+(..)141520 VVMAXACMAX=´2In addition to VMAX+VOR the drain also sees a large voltage spikeat turn off that is caused by the energy stored in the leakageDSS, a clamp circuit is neededacross the primary winding. A Zener clamp as shown inCLO needs to be 50% (determined empirically) greater than thereflected voltage so that the Zener clamps only the leakage tC PO = Output Power\r\r fL = Line Frequency\r\t\t\t\t\t (50 or 60Hz)\rC = Conduction Angle\r Use 3ms if unknown\rh = Efficiency - Assume\r\r\r VVACMINMIN´2 =´-()( V+Figure 7. Input Voltage Waveform. A6/96 AN-1613 PI-1853-050696 15 VRTN BR1\r400 VC1\r47 mF\r400 VC5\r47 mFC4\r0.1 mFU1\rTOP204YAIR3\r6.2 WR2\r200 W\r1/2 WD2\rMUR610CTD3\r1N4148C2\r1000 mF\r35 VT1D1 C7\r1 nF\rY1 DRAINSOURCECONTROL C3\r120 mF\r25 V U2\rNEC2501U3\rTL431R4\r49.9 kWR5\r10 kW C9\r0.1 mFR1\r510 WVR1 L1\r3.3 mH F1\r3.15 AJ1C6\r0.1 mFL2\r33 mHL\r \rN Figure 6. ST204A Reference Design Board.a corresponding pay back in terms of higher VMIN or lowerripple, whereas lower values of CIN result in significantly lowerVMIN increasing TOPSwitch cost due to increased peak operatingcurrent demand. Lower values of CIN also increase input ripplevoltage, which could increase output ripple voltage if thecontrol loop gain is a limiting factor.The accurate calculation of VMIN for a given CIN (or vice versa)is a very complicated task which involves the solving of anequation with no closed form solution. The equation shown =´-Step 4.Determine reflected output voltage VStep 3.Determine input capacitor CF/Watt for 230VAC. This results in a V AN-16 A6/96 12Figure 4. RD1 Reference Design Board (Enhanced).Figure 5. ST202A Reference Design Board. PI-1851-050696 +5VRTN C1\r10nF\r400 VC5\r47 mF\r10 VC4\r100 nF\r50 VD2\r1N5822D3\rBAV21C2\r330 mF\r10 VT1D1 C3\r100 mF\r10 V R1\r15 WVR1\r\r L1\r3.3 mH U1 DCSSTOP\r210 VR 2\r1N5251D\r22 V\r1% \r213458\r +-DC\rINPUTTRD1-1 PI-1852-050696 7.5 VRTN C5\r47mFD2\rUG8BTD3\r1N4148R2\r68 WVR2\r1N5234B\r6.2 VC3\r120 mF\r25 VT1D1 C2\r680 mF\r25 V VR1 BR1\r400 VC1\r33 mF\r400 V R1\r39 WU2\rNEC2501 U1\rTOP202YAI DRAINSOURCECONTROL C4\r0.1 mF C7\r1 nF\rY1 L1\r3.3 mH F1\r3.15 AJ1C6\r0.1 mFL2\r22 mHL\r \rN \r A6/96 In-depth InformationStep 2.Decide on a Feedback/sense circuit and biasaccuracy can be improved for the primary feedback circuit by PI-1850-050696 +5VRTN C1\r10 nF\r400 VC5\r47 mF\r10 VD2\r1N5822D3\r1N4148C2\r330 mF\r10 VT1D1\r\r C3\r100 mF\r10 V R1\r15 WVR1 L1\r3.3 mH +-U1 DCSS TOP\r210 213458DC\rINPUT\rTRD1 AN-16 A6/96 Step 28. to Step 29.Add output LC post filter if and only if output switching ripple voltage is not within specification:¥ Capacitor, C:120uF, 35V, low ESR electrolytic VPFRectifierV(V)Manufacturer1N414875MotorolaBAV21200PhilipsUF4003200GI Table 9 A6/96 OutputOutput Capacitor 5V to 24V, 1A330uF, 35V, low ESR, electrolytic 5V to 24V, 2A1000uF, 35V, low ESR, electrolyticRectifier DiodeV (V)I(A)ManufacturerSchottky 1N5819401.0Motorola 1N5822403.0Motorola MBR745457.5Motorola MBR10454510Motorola MBR16454516MotorolaUFR UF40021001.0GI MUR1101001.0Motorola MUR1202001.0Motorola UF40032001.0GI BYV27-2002002.0Philips, GI UF54011003.0GI UF54022003.0GI MUR4101004.0Motorola MUR4202004.0Motorola MUR8101008.0Motorola MUR8202008.0Motorola BYW29-2002008.0Philips, GI BYV32-20020020Philips AN-16 A6/96 ¥ Set safety margin, M. Use 3 mm (118 mils) for margin wound(B28) 2000; in Gauss(D48) 0.051 mm(D51) 200;(D58)¥ Primary minimum conductor diameter, DIA: in mm(D55)¥ Primary maximum wire outside diameter, OD: in mm(D53)SP, S, SP RIPPLE Notes: 1. P6KE91:91V/5W; Motorola P6KE200:200V/5W; Motorola BYV26B:400V/1A, UFR; Philips BYV26C:600V/1A, UFR; PhilipsInput (VAC)V(V)ZenerDiode100/11590P6KE91BYV26BUniversal200P6KE200BYV26C230200P6KE200BYV26C Table 7 BM Lg CMAL­--­ (B29)NS­¯­¯ (B30)Core­¯­­ (B24/25/26/27) Table 6 A6/96 AVG RMS using AN-18 Appendix A, Table 2 and determine A 2.0 throughout iteration)(B29) AN-16 A6/96 0.6 for 230 VAC Table 3VMIN (V)³90³90³Input (VAC)CIN (mF/Watt of PO)2~3Input (VAC) Table 4 Minimum Table 5Input (VAC)100/115Universal MaximumKRPVOR (V)60VCLO (V)90 A6/96 : 0.8 if no better reference data available(B9) FeedbackOutput LoadLineReferenceCircuitVAccuracy RegulationRegulationDesignPrimary/basic 5.710% 1.5%RD15% 1.5%RD1Opto/Zener125% 0.5%ST202AOpto/TL431121% 0.2%ST204A Table 2 AN-16 A6/96 4Step 25-35\rSelect Other Components From Step 24 NY 25. Select Clamp Zener & Blocking Diode27. Select Output Capacitor28. Switching Ripple\rToo High29. Select Output Post Filter L, C30. Select Bias Rectifier31. Select Bias Capacitor 32. Select Control Pin Capacitor\r& Series Resistor33. Select Feedback Circuit Compenents\rAccording to Reference Designs:\rRD1, ST202A, ST204A34. Select Bridge Rectifier35. Design\r Complete\r 26. Select Output Rectifier PI-1870-052896Figure 2C. TOPSwitch Flyback Design Flow Chart, Step 25 to 35. A6/96 AN-163 13. Choose Core & Bobbin\r\t\t\t\t\t\tDetermine Ae, Le,AL, BW14. Set NS, L15. Calculate NP, NBY 22. NS, L Iterated 16. Calculate BM \r To Step 25Step 12-24\rDesign The Smallest Transformer\rTo Work with The TOPSwitch Chosen 23. Calculate ISP, ISRMS, IRIPPLE\rDIAS, ODS24. Calculate PIVS, PIVBN 12. Determine LP NYNYNY 17. 2000 £ BM£ 300018. Calculate Lg19. Lg � 0.051 mm20. Calculate OD, DIA, CMA21. 200 £ CMA £ 500 From Step 11PI-1869-052896The overriding objective of this procedure is Òdesign for costeffectivenessÓ. Using smaller components will usually lead tostrike a compromise between cost and specific designFigure 2B. TOPSwitch Flyback Design Flow Chart, Step 12 to 24. AN-16 A6/96 2 1. System Requirements\rVACMIN, VACMAX, fL, VO, PO, h, Z 2. Choose Feedback Circuit & VB3. Determine CIN, VMIN4. Determine VOR, VCLO5. Determine DMAX6. Set KRP7. Determine IAVG, IP, IR, IRMS8. Choose TOPSwitchYN \r9. Calculate TOPSwitch loss PD 10. PD Too HighNY To Step 12Step 1-2\rDetermine System Level Requirements\rand Choose Feedback Circuit11. IP= 0.9 x ILIMIT \ror\rKRP= 1 Step 3-11\rChoose The Smallest TOPSwitch\rFor The Required Power power supply output requirement, one of four possible circuits,shown in Figures 3-6, will be chosen for the application.1.Determine system requirements and decide on feedback2.Find the smallest 3.Design the smallest transformer for the 4.Select all other components in Figure 1 to complete the June 1996 Application Note AN-16 FUSECM\rCHOKEVACCXV++VD-+VDB-Clamp ZenerBlocking DiodeV-PI-1849-050696VOCIN +-VB+ -TOPSwitch Output Capacitor Output Post Filter L, C Bias CapacitorControl Pin Capacitor \rand Series Resistor Feedback Circuit DRAINSOURCECONTROL

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