PPT-Does Hardware Transactional Memory Change Everything?

Maurice Herlihy Computer Science Dept Brown University 2 Not important The details Important Irrevocable change 3 How to think about Synchronization Poor synchronization ruins everything. tumde Abstract So far transactional memoryalthough a promising techniquesuffered from the absence of an ef64257cient hardware implementation The upcoming Haswell microarchitecture from Intel introduces hardware transactional memory HTM in mainstream FernandesJoaoCachopo istutlpt Abstract Software Transactional Memory STM was initially propose d as a lockfree mechanism for concurrency control Early imple menta tions had ef64257ciency limitations and soon obstructionfre e propos als appeared to ta Gokarna. Sharma. Costas Busch. Louisiana State University, USA. WTTM 2010 - 2nd Workshop on the Theory of Transactional Memory. 1. TexPoint fonts used in EMF. . Read the TexPoint manual before you delete this box.: . Memory. Supporting Large Transactions. Anvesh. . Komuravelli. Abe Othman. Kanat. . Tangwongsan. Hardware-based. . Concurrent Programs. obj.x. = 7;. find_primes. ();. // intrusion test. if (. obj.x. On the Interplay of Hardware Transactional Memory and Lock-free Indexing. Justin . Levandoski. Microsoft Research Redmond. Ryan Stutsman. Microsoft Research Redmond. Darko. . Makreshanski. Department of Computer Science. Rajwar. , R., . Herlihy. , M., and Lai, K. 2005. presented by . VasilyVolkov. , 04/30/08. Motivation. Transactional Memory is good. Never deadlocks. Makes concurrent programming easier. But requires programmer to be aware of. Patrick Santos (4465359). 1. Agenda. What is transactional memory (TM)?. Example transactions. Deadlocks and Cache Coherence. Types of TM. Implementations . & proposals . in industry. Sun / Oracle. Maurice Herlihy (DEC), J. Eliot & B. Moss (UMass). Presenter: Mariano Diaz. CS 5204 – Fall, 2009. Part 1: Concepts and Hardware-based Approaches. Introduction. What’s a transaction?. Transaction: a finite sequence of machine instructions, executed by a single process, that satisfies the following:. Prof. Smruti R. Sarangi. IIT Delhi. Outline. Multicore Processors. Parallel Programming Pardigms. Transactional Memory: Basics. Software Transactional Memory(STM). Hardware Transactional Memory. Multicores in the last Five Years. Prof. Smruti R. Sarangi. IIT Delhi. Outline. Multicore Processors. Parallel Programming Pardigms. Transactional Memory: Basics. Software Transactional Memory(STM). Hardware Transactional Memory. Multicores in the last Five Years. Hardware vs. Software. Hardware includes. CPU = central processing unit. Memory = RAM (random access memory). Input = Keyboard, mouse, microphone. Output = Screen, speaker, printer. Storage = Hard drive, DVD, Solid State. CSE351 Autumn2011. 1. st. Lecture, September 28. Instructor:. . Luis Ceze. Teaching Assistants:. Nick Hunt, Michelle Lim, Aryan . Naraghi. , Rachel . Sobel. 1. 2. Who is Luis?. PhD in architecture, . Serdar . Tasiran. Koc University, Istanbul, . Turkey. Microsoft Research, Redmond. Hassan . Salehe. . Matar. ,. . Ismail . Kuru. , . Koc University, Istanbul, Turkey. Roman . Dementiev. Intel, Munich, Germany. Alvaro Moreira & Luigi Carro. Instituto de Informática – UFRGS . Brasil. 1. Outline – Part III. Work . done at UFRGS on . detection/correction . of . Control Flow Errors (CFEs) with LLVM. Similarities and differences with Security.