Microcomputer Architecture This lectur gives an overvie of the ar hitectur of simple micr ocomputer It describes the oper ation of the CPU addr ess and data uses during ead and write cycles
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Microcomputer Architecture This lectur gives an overvie of the ar hitectur of simple micr ocomputer It describes the oper ation of the CPU addr ess and data uses during ead and write cycles

After this lectur you should be able to 1 show how the following uses and signals ar connected in micr o computer system power and gr ound addr ess and data uses ead and write str obes and hip enables 2 give the sequence of signals that must appear

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Microcomputer Architecture This lectur gives an overvie of the ar hitectur of simple micr ocomputer It describes the oper ation of the CPU addr ess and data uses during ead and write cycles




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Presentation on theme: "Microcomputer Architecture This lectur gives an overvie of the ar hitectur of simple micr ocomputer It describes the oper ation of the CPU addr ess and data uses during ead and write cycles"— Presentation transcript:


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Microcomputer Architecture This lectur gives an overvie of the ar hitectur of simple micr ocomputer It describes the oper ation of the CPU addr ess and data uses during ead and write cycles. After this lectur you should be able to: (1) show how the following uses and signals ar connected in micr o- computer system: power and gr ound, addr ess and data uses, ead and write str obes, and hip enables; (2) give the sequence of signals that must appear on the addr ess, data, and contr ol lines of memory or I/O hip in or der to ead or write particular data value to/fr om particular

addr ess; (3) xplain the purpose of these lines; and (4) compute the number of addr ess lines equir ed for given memory size or vice-versa. Micr ocomputer Components microcomputer is usually assembled from micro- processor chip (CPU connected to memory chips and I/O (input/output chips. signal is oltage or current that transfers infor mation within circuit. us is group of related signals. The follo wing diagram sho ws the two most im- portant uses in typical microcomputer The thick lines sho ws uses and the arro ws indicate whether the signal is an input, output or as in the case of the data

us, if it can alternate between the two direc- tions. CPU Memory I/O Address Bus Data Bus Memory Memory chips are digital logic de vices used in mi- crocomputer systems to store programs and data. It is necessary to understand ho the work in order to understand the operation of microcomputer There are two main types of memory chips: OM and RAM. The contents of OM (read-only mem- ory) chip can only be read. The contents of RAM (random access memory) chip can be read and writ- ten. The adv antage of OM is that, unlike RAM, it contents are retained when po wer is remo ed. Ex ercise: Is RAM chip

combinational circuit or sequential circuit? Ho about OM chip? Central Processing Unit OM operates like an array Each element of the array corresponds to one storage element in the memory chip. The address input to the chip is used to select particular memory location (corresponding to the array inde x). The alue read from the mem- ory chip corresponds to the content of the selected element of the array Address Data ROM Ex ercise: Ho wide is the address us on 64 kByte 16 yte) yte-wide (64k imes 8) OM? Ho wide is the data us? There are man types of OM chips. The most common are EPR OMs

(erasable programmable read- only memory) which can be erased by xposing them to strong ultra-violet light for se eral min- utes and then re-written using de vice called de- vice programmer EEPR OMs (electrically erasable programmable read-only memory) are similar to EPR OMs, ut the can be quickly erased by the de- vice programmer before being re-programmed. The diagram belo sho ws the signal pins on typ- ical RAM chip: WR (write strobe) RD (read strobe) address bus data bus power ground RAM enable As with an other logic de vice, it has po wer and ground pins. In RAM the address us is an input

that is used to tell the memory chip which address is being accessed. The data us is used to con the data between the CPU and the RAM. It is ˚bi- directional us since it is an input during write op- eration and an output during read operation. There lec6.tex
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is also an ˚enable input that must be high for the RAM to do an ything at all. The CPU-R OM interface is similar to that for RAM xcept that there are no pro visions to write to it. Ex ercise: ould OM ha wr ite strobe (WR) input? There are two main types of RAM chips. Static RAM (SRAM) chip storage their state

in ˇip-ˇops while dynamic (DRAM) chips store their state as the char ge in capacitor This makes DRAM chips sim- pler and cheaper than SRAM chips ut their contents need to refreshed periodically CPU This section describes the functions of the signals ap- pearing on the pins on the CPU chip. The follo wing diagram sho ws the input and output signals on typ- ical CPU. WR (write strobe) RD (read strobe) address bus data bus CPU clock power ground RESET As with an other digital logic chip, the CPU chip needs pins to supply po wer and ground. The CPU also needs clock signal (a signal that

periodically switches from high to lo w). This clock input is used by the processor to synchronize its internal opera- tions. The processor is (v ery complicated) state machine and the clock is used to sequence between the processor states. The clock speed typically ranges from 32 kHz to se eral hundred MHz. The chip has two uses: the address us and the data us. These two uses are used by the processor to communicate with memory and I/O chips. An address us of bits can be used to select (ad- dress) one of bytes in the microcomputer mem- ory ypical address us sizes (˚widths) are 16 bits

(most 8-bit microprocessors), 20 bits (the 8088 CPU used in the original IBM PC), 24 bits (the 68000 CPU used in the lab computer) and 32 bits (the chips used in modern microprocessors). The indi vidual signals in the us are usually gi en the labels Ex ercise: Appro ximately ho man ytes can each of the abo processors address? Hint: Use the appro ximation that 10 is about 1000 The data us is used to transfer data between mem- ory or I/O peripherals and the CPU. The data us width in modern computers is always an en mul- tiple of bits. or simplicity we will only consider CPUs with an 8-bit data

us width. The indi vidual signals in the data us are usually gi en the labels The address and data uses connect the CPU to the memory and I/O chips. Multiple memory de vices can be connected in parallel to these uses ut ad- ditional logic circuitry (˚address decoders) are re- quired to ensure that only one de vice is enabled at time. Finally there are number of control signals. will only consider three of these: the read and write strobe outputs (RD and WR), and the RESET input. The RD and WR outputs are used to control mem- ory de vices. If the RD output is high, the CPU is reading from

memory (a ˚read ycle); if the WR output is high the CPU is writing to memory (a ˚write ycle). The RESET input pin resets the processor to kno wn initial state. This is usually done when po wer is ˛rst applied or if the processor gets stuck while ecuting uggy program. When the RESET pin is brought high the processor stops ecuting the cur rent instruction sequence and restarts ecution at an address that contains program to restart the com- puter Read and Write Cycles The follo wing diagram sho ws the signals on OM or RAM during read ycle. Address Bus Data Bus Read Strobe next

cycle The follo wing operations take place during read operation (˚c ycle): the CPU puts the address of the desired memory location on the address us (1) the CPU turns its data us into an input (2)
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the CPU asserts (brings high) the RD signal line (3) the RAM detects the high signal on the RD line and turns its data us into an output (4) the RAM looks up the alue current alue stored for that memory location and, after short delay (the access time), outputs it on the data us (5) the CPU read the alue from the memory (6) The follo wing table sho ws the alues of the dif fer

ent signals er time during read ycle where the CPU reads the alue 0x32 from address 0x105: address data RD WR us us 0x105 0x105 0x105 0x32 The follo wing operations take place during write ycle: the CPU puts the address of the desired memory location on the address us the CPU turns its data us into an output the CPU puts the alue to be stored on the data us the CPU asserts (brings high) the WR signal line the RAM detects the high signal on the WR line and turns its data us into an input the RAM stores the alue currently on the data us into the desired memory location inside the RAM Ex ercise:

Dra timing diagram and wr ite out tab le similar to those abo sho wing the alues appear ing on the two strobes and the address and data uses when the alue 0x33 is wr itten to address 0x1200. I/O Chips I/O chips are used to allo the CPU to interface with peripherals (ke yboards, printers, etc). An output I/O chip consists of ˇip-ˇops which are loaded during write ycle. The ˇip-ˇops in- puts (D) are connected to the data us and the outputs (Q) are connected to the peripheral. When the CPU writes to the memory location that clocks the ˇip- ˇops, the

ˇip-ˇops are loaded and the alues written to them remain on the output pins. An input chip is simply uf fer that causes the alue currently on the input pins to be transferred to the CPU. This allo ws the CPU to monitor the state of the input pins on the I/O chip. The follo wing diagram sho ws the internal struc- ture of simple parallel i/o chip: Address Bus Data Bus decoder Address Bus Read Strobe decoder Write Strobe Data Bus There are man dif ferent I/O chips ailable. The usually include additional logic circuits to make it easier for the CPU to deal with speci˛c peripherals

such as modems or hard disks. Later in the course we will look at fe common interface chips. The follo wing diagram sho ws the xternal inter face of an i/o chip: WR (write strobe) RD (read strobe) address bus power ground output pins input pins I/O peripheral peripheral enable Addr ess Decoders microcomputer often uses se eral memory and I/O chips, each of which is smaller than the total amount of memory that the microprocessor (CPU) can ad- dress. or xample, CPU with with 16-bit address
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us can address 64 kBytes of memory ut may be used in system with 16 kByte RAM, 32 kByte

EPR OM and 4-byte I/O chip. Ex ercise: Ho man address lines are required each of the abo chips? The purpose of the address decoder is to look at the address output by the CPU and enable indi vidual memory or I/O chips. The follo wing diagram sho ws the inputs and outputs of an address decoder: address bus power ground enable enable enable Address Decoder Ex ercise: Dra diagram sho wing ho CPU with an 8-bit data us and 20-bit address us two 8k RAMs 64k EPR OM, an I/O chip with inter nal one-b yte por ts and ar i- ous address decoders would be connected to uild microcom- puter Sho the

connections of the data and address uses and the read and wr ite strobes Use arro ws at each chip to indicate whether par ticular signal is an input or an output. Indicate the width of each us and the range of the address us signals used each chip Micr ocontr oller microcontroller is single-chip microcomputer One chip includes the CPU, RAM, an I/O chip and an EPR OM or EEPR OM. This allo ws all of the pins on the chip to be used for I/O.