Chi Hierarchical Instructions: Reusable Compiler

Extract CHI from Taichi 5 CHI Any Frontend IR Builder<br>

Why CHI? Portability
High performance
Taichi features:
Sparse programming
Differentiable programming
Quantization
… 6 No need of pybind11 No need of Python frontend Standardization<br>

Statements 7<br>

IR Builder An interface to generate CHI IR conveniently
Example: generate 40 + 2: 8 auto block = std::make_unique<Block>();
auto func = []() {};
auto kernel = std::make_unique<Kernel>( get_current_program(), func, "fake_kernel");
block->kernel = kernel.get();
auto *lhs = block->push_back<ConstStmt>( TypedConstant(40));
auto *rhs = block->push_back<ConstStmt>( TypedConstant(2));
auto *add = block->push_back<BinaryOpStmt>( BinaryOpType::add, lhs, rhs); Before IRBuilder builder;
auto *lhs = builder.get_int32(40);
auto *rhs = builder.get_int32(2);
auto *add = builder.create_add(lhs, rhs); After<br>

Loop guards “Chi Hierarchical Instructions”
Handle insertion points automatically
WYSIWYG 9 IRBuilder builder;
auto *zero = builder.get_int32(0);
auto *ten = builder.get_int32(10);
auto *loop = builder.create_range_for(zero, ten);
{
auto _ = builder.get_loop_guard(loop);
auto *index = builder.get_loop_index(loop, 0);
}
auto *ret = builder.create_return(zero); kernel {
<i32> $0 = const [0]
<i32> $1 = const [10]
$2 : for in range($0, $1) {
$3 = loop $2 index 0
}
$4 : kernel return $0
}<br>

Interaction with C++ arrays Example: a[1] = a[0];




Declare kernel arguments & run on backends! 10 auto *arg = builder.create_arg_load(/*arg_id=*/0, get_data_type<int>(), /*is_ptr=*/true);
auto *zero = builder.get_int32(0);
auto *one = builder.get_int32(1);
auto *a0 = builder.create_global_load(builder.create_external_ptr(arg, {zero}));
builder.create_global_store(builder.create_external_ptr(arg, {one}), a0); auto ker = std::make_unique<Kernel>(prog, builder.extract_ir());
ker->insert_arg(get_data_type<int>(), /*is_external_array=*/true); // int *
auto launch_ctx = ker->make_launch_context();
launch_ctx.set_arg_external_array(/*arg_id=*/0, (uint64)a, size); // int a[size];
(*ker)(launch_ctx); // run!<br>

Key compilation passes 11 Type checking
(Optional) Automatic Differentiation
Automatic Parallelization (Offload)
Lower access

(And many optimization passes)<br>

Lower access ti.root.pointer(ti.i, 4).dense(ti.i, 2).place(x) 12 <i32> $1 = const [0]
<*f32> $2 = global ptr [S3place<f32>], index [$1] activate=true <i32> $1 = const [0]
<*gen> $3 = get root
<*gen> $4 = [S0root][root]::lookup($3, $1) activate = false
<*gen> $5 = get child [S0root->S1pointer] $4
<*gen> $6 = [S1pointer][pointer]::lookup($5, $1) activate = true
<*gen> $7 = get child [S1pointer->S2dense] $6
<*gen> $8 = [S2dense][dense]::lookup($7, $1) activate = false
<*f32> $9 = get child [S2dense->S3place<f32>] $8 6 root pointer 1 dense 1 0 0 2 4 0 1 2 3 4 5 6 7 place x 0 Lower access<br>

Analysis manager Atomic demotion for bit struct stores needs to gather all uniquely accessed bit structs.
Gather uniquely accessed bit structs must be before lower access since the latter will corrupt some information for aliasing analysis.
Atomic demotion for bit struct stores must be after lower access since bit struct stores are generated from the lowered accesses for now. 13 Information?<br>

Pass manager? Customize compilation passes
Use function interface (instead of class in LLVM/TVM/SPIR-V/…)for passes (functions)



Typical API for now:bool my_foo_pass(IRNode *ir, const CompileConfig &config, AnalysisManager *amgr, const MyFooPass::Args &args); 14 irpass::type_check(ir, config);
irpass::full_simplify(ir, config, {/*after_lower_access=*/false, kernel});
irpass::check_out_of_bound(ir, config, {kernel->name});
...<br>

Summary Standardize CHI IR
Generate CHI IR: IR Builder
Pass analysis information across passes: Analysis manager
Customize compilation passes: call functions directly

Towards a portable and high-performance compiler infrastructure for visual computing! 15<br>