Introduction to VHDL Coding Wenchao Cao, Teaching

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Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee Outline Example of VHDL Coding in Xilinx ISE Design Suite Basic Knowledge of VHDL Outline Example of VHDL Coding in Xilinx ISE Design

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Introduction to VHDL Coding Wenchao Cao, Teaching Assistant
Department of EECS
University of Tennessee

Outline Example of VHDL Coding in Xilinx ISE Design Suite
Basic Knowledge of VHDL

Example of VHDL Coding in Xilinx ISE Design Suite Work Flow
The figure shows the software tools in a logic design project from schematic to VHDL code to *.bit file for download to BASYS or BASYS2 board.

Implementation of a Full Adder

Create A New Project

Project Settings Choose TQ144 if you are using a BASYS board

Create New Sauce Files

Generated VHDL file template by the software:

Entity declaration
(Entity name)
Port definition
(Port name and direction)
Architecture body
(Write the functions here!)

Outline Example of VHDL Coding in Xilinx ISE Design Suite
Basic Knowledge of VHDL

Entity declarations
Entity identifier: Lab00

Ports definition
Port names: A, B, Cin, S, Cout
Port directions
“in” for input ports, “out” for output ports.

Architecture body
Architecture identifier: Behavioral

Behavioral descriptions
Signal assignment statement
S <= A xor B xor Cin;
Logical operators
and, or, not, xor, nand, nor, xnor
(No difference between upper case and lower case.)
Use ( ) to make the statement clearly expressed. Basic Modeling Constructs

Example Signal Assignment Statement Logical operators in lower case Logical operators in upper case Less parentheses ( )

Example Assign Logic ‘1’ and Logic ‘0’ Assign value of ‘1’ Assign value of ‘0’

Introduction to VHDL Coding QUESTIONS ?

Introduction to VHDL Coding Wenchao Cao, Teaching

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