Two FPGA Case Studies Comparing High Level

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Two FPGA Case Studies Comparing High Level Synthesis and Manual HDL for HEP applications Marc-André Tétrault IEEE NPSS Real Time Conference 2018 Williamsburg Overview Whatwhy High Level Synthesis (HLS) First contact account Signal

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01
Two FPGA Case Studies Comparing High Level Synthesis and Manual HDL for HEP applications Marc-André Tétrault
IEEE NPSS Real Time Conference 2018
Williamsburg<br>
02
Overview What/why High Level Synthesis (HLS)
First contact account
Signal processing design
Flow-through event sorting engine
Take home message IEEE NPSS Real Time Conference 2018 - Williamsburg 2<br>
03
Hardware Description Language (VHDL) process(clk)
begin
if (clk'event and clk = '1')then
q_ResetBLine <= Control(1) xor Control(2);
q_MeanBLine <= Control(2) xor Control(c_Size - 1);

if(q_ResetBaseline = '1')then
q_MeanAcc <= "00" & i_EventStream;
elsif(q_MeanBaseline = '1') then
q_MeanAcc <= q_MeanAcc + i_EventStream;
end if;
end if;
end process; High Level Synthesis (C/C++) int BaseLineMean(int Samples[], int ReturnSamples[])
{
int Mean = 0;
for(int x= 0 ; x < SAMPLE_COUNT; x++)
{
if(x < 4) Mean += Samples[x];
ReturnSamples[x] = Samples[x];
}
Mean >>= 2; // divide by 4
return Mean;
} What is High Level Synthesis Additional declarations and flow control sections IEEE NPSS Real Time Conference 2018 - Williamsburg 3 Example process:
Average of first 4 samples Additional directives to HLS compiler<br>