CS345 David Monismith Based upon notes by Dr Bill Siever and notes from the Patternson and Hennessy Text Recall Recall that the RSLatch allows for storage of a single bit through the use of either ID: 487787
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Slide1
Computer Organization
CS345
David
Monismith
Based upon notes by Dr. Bill
Siever
and notes from the
Patternson
and Hennessy TextSlide2
Recall
Recall that the RS-Latch allows for storage of a single bit through the use of either
two NOR
(not OR) gates or two NAND (not AND) gates
.
Last
time
We
learned that the RS latch allows for storage by feeding the outputs Q and ~Q back into the NAND or NOR gates.
On
inputs of R = 1 and S = 0, the value stored is reset to 0. That is Q = 0.
This
resets the latch.
On
inputs of R = 0 and S = 1, the value stored is set to 1. That is Q = 1.
This
sets the latch.
On
inputs of R = 0 and S = 0, the value stored is not modified.Slide3
Recall
Recall that performing both a set and a reset at the same time is an invalid operation and will result in an oscillating state. It is possible to recover from this state by attempting to set and reset the latch, but it will take time to recover
.
The
minimum time required to recover from an oscillating state is the time to change the signal plus the propagation delay required for the inputs to feed back through the gates.Slide4
Oscillation Prevention
We will look at methods to prevent oscillating states from occurring.
Since
an RS-Latch should never have both R and S set to one, we could attempt
to create
additional logic to prevent such a state from ever occurring.
To do so, we will add two AND gates immediately prior to the latch The outputs from these AND gates will be the inputs to the RS-Latch for R and S, respectively.Slide5
Oscillation Prevention
Changing the meaning of our inputs
Instead
of using set and reset as inputs we will now pretend to use two inputs called D and E.
E
is provided as input to both AND gates.
D is provided as an input to the first AND gate. ~D is provided as input to the second AND gate.
By providing D to the first AND gate as an input and ~D to the second AND gate, the outputs from the AND gates representing set and reset can never both be true at the same time.Slide6
Oscillation Prevention contd.
D is a signal used to change the data stored.
If
D is one, we change the value stored in the latch.
That
is, if one was stored
in the latch, the value stored would be changed to zero. If zero was stored in the latch, the value stored is changed to one. E
is a signal used to enable or disable the latch. If E is one, changes may be made to the value stored. If E is zero,
no changes may be made to the value stored. Now, D works like a push-button. When D is one or we push the button for D, the value stored changes.
E
works like an on/off switch. When E is on we can modify the latch.Slide7
D
Latches
The type of latch describe above is called a D-Latch.
It
is also known as a
Level Triggered Flip Flop.
A D-Latch contains an RS-Latch, thus it can store one bit.Initially the value stored will oscillate if no signal is provided as input.
Stabilization occurs after an initial input is provided for both Enable and Data inputs. Slide8
D
Latch
The D-Latch has an interesting property that can be observed
.
While the latch is enabled, the value stored may be changed
.It
is because of this property that the D-Latch is sometimes referred to as a Level-Triggered Flip Flop. Notice that any time the signal on the D line meets the same level
as the signal on the E line, while E is one, the value stored will change. Any time E is "off" or zero, the value stored will remain constant.
Hence the name level triggered.Slide9
JLS D
Latch
A gate-based example of a D-Latch is available on the examples page of the
class website
.
JLS provides a component based model of a D-Latch, too.
+-------------+D input --> | D Q |
--> Q output | | |
\ |E input --> |C > ~Q | --> ~Q output
|
/
|
+--------------+
Notice
that in the component based representation none of the gates are visible.Slide10
D
Latch
Only the inputs and outputs are
accessible. This
provides the abstraction
necessary to utilize many D-Latches as registers.
Notice that a 32 bit register could be represented by 32 D-Latches.Next time we will look at another type of flip flop called an edge-triggered flip flop that only changes state with either the rising or falling edge of the enable input.