PPT-Timing Analysis

in a Mixed Signal World TAU Workshop Panel Session Jim Sproch March 12 2015 Are Existing Delay Models Useful for Mixed Signal Timing Analysis Mixed signal designs comprise a mix of digital analog and analogish circuits. Tsung. -Wei Huang. and Martin D. F. Wong. Department of Electrical and Computer Engineering (ECE). University of Illinois at Urbana-Champaign (UIUC), IL, USA. 2015 ACM International Symposium on Physical Design (ISPD). Subramanyam. Sripada. Synopsys . Inc. 3/13/2015. Constraint Analysis/Debug/Management. Budgeting Issues. Functional. Scan. Test. Low_Power. More Modes. More Files/. More complex. constraints. IP Blocks. PrimeTime. . Speaker: Bob Tsai. Advisor: . Jie. -Hong Roland Jiang . Introduction. Flow. On Chip Variation (OCV). Manual/automated . netlist. editing. Signal integrity and crosstalk. Outline. PrimeTime. Recovery . With . Flexible . Flip-Flop Timing . Model. Andrew B. Kahng and . Hyein Lee. UC . San . Diego VLSI CAD Laboratory. Outline. Preliminary. Motivation. Related Work. Sequential LP-based Optimization. Objectives. After completing this module, you will be able to:. Describe a flow for obtaining timing closure. Interpret a timing report and determine the cause of timing errors. Apply Timing Analyzer report options to create customized timing reports. Qiuyang Wu. 2015.3.13. Outline. This talk answers the following questions regarding timing constraints:. What are the key scalability challenges?. What are the available solutions?. Design Complexity Trends. PrimeTime. Introduction. Static Timing Analysis tool. Static Timing Analysis . : Determines whether the design works at the required speed.. PrimeTime. ASIC design from Design Compiler. Layout Verilog from IC Compiler. Sam Appleton, CEO. CONFIDENTIAL. Challenges in SDC Creation & Verification. It can get a bit messy . “IP”/block level timing. Making sure design is fully constrained. Finding balance between timing exceptions and risk. Static Timing Analysis. Tom Spyrou . TAU 2013. 3/2013. Goal of this talk. Higher level than latest trends. Remind ourselves the trade-offs we have made as an industry to have a workable solution for STA. Tsung. -Wei Huang. and Martin D. F. Wong. Department of Electrical and Computer Engineering (ECE). University of Illinois at Urbana-Champaign (UIUC), IL, USA. 2015 ACM International Symposium on Physical Design (ISPD). Laser / RF Timing ( E ngineering of Femtosecond Timing Systems) Josef Frisch SLAC Femtoseconds Bryan Bandli , Scanning Electron Microscopy Laboratory, University of Minnesota 70fs Eye blink ½ human hair CIRCUIT CELLAR® er, I’ve noticed that many electricalthem quite complex, but they haven’t waveforms indicate the uncertainty ofuncertainty, because the uncertainty2. Note that the waveform Andrew B. Kahng. +$. , . Uday Mallappa. $. . and . Lawrence Saul. +. UC San Diego . $. ECE & . +. CSE Department. Preliminaries . Modeling Features. Modeling Methodology. Experiments . Conclusions. With . Flexible . Flip-Flop Timing . Model. Andrew B. Kahng and . Hyein Lee. UC . San . Diego VLSI CAD Laboratory. Outline. Preliminary. Motivation. Related Work. Sequential LP-based Optimization. Experimental Results.