Timing Analysis - PowerPoint Presentation

Slide1

Timing Analysis in a Mixed Signal WorldTAU Workshop Panel Session

Jim Sproch

March 12, 2015Slide2

Are Existing Delay Models Useful forMixed Signal Timing Analysis?Mixed signal designs comprise a mix of digital, analog, and analog-ish circuits

Partitioning ideally puts model boundaries at a digital interface

Existing delay modeling syntax and semantics were designed for digital circuit applications

Some properties are transferrable to mixed signal

Capacitance, pulse noise, voltage swing, current source/sinkSome analog mixed signal properties are absentGain, bandpass, analog noise, frequency response, jitter, phase error, acquisition and tracking range

PrechgB

Wmux

WmuxB

R

muxB

Rmux

SA-PrechgB

SAenable

DataOut

WL-0

WL-NSlide3

Abstract Models for Mixed SignalEncapsulation of function and key interface parametersFunctionality, timing, noise, variation (LVF), drive strength

Electromigration (EM), pin load capacitance, static/dynamic power

Liberty™ open-source standard for library models

N

on-linear table format (NLDM)Current-source format (CCS, ECSM)Diverse industry participation via LTABComplementary interoperability with IEEE-1801 (UPF, CPF) power intent standardSlide4

Do Models Work for Mixed Signal?Model interfaces are a challenge for even digital circuitsNon-linear waveform effectsSimultaneous, or near-simultaneous switching

Complex input impedance

Models do add value for mixed signal designs

Encapsulation in a black box model for hierarchical verification

Pin-to-pin arcs to support timing propagationTechnical challenges External cross-talkImpedance shieldingComposite and macro modelingSlide5

Transistor-Level Static Timing AnalysisSTA for custom digital and interface circuitsHierarchical SPICE netlist and transistor model card input

Exhaustive, vector-free verification of digital timing constraints

Support for digital circuits in an analog context, e.g. DCVSL,

SerDes

Support for memories and particular analog-ish circuit topologiesTiming constraint coverageComplete set of combinational and sequential checksSetup, hold, recovery, removal, min pulse widthMixed-signal checks include Differential clock and data signals, sense amp enable, synchronizers, precharge, level shifters, contention resolutionUltra-fast custom digital circuits: Verilog-A monitor in every DFF instanceCharacterization to encapsulate in a Liberty extracted timing modelTechnical challengesFull analog circuits, PLL, ADC, DAC, switch-cap, LRC

LVsig

HVsig

VddL

VddHSlide6

Co-Simulation for Mixed Signal DesignsCombine SPICE with a logic simulator

Functional,

timing,

and power-up simulation

High throughputExcellent accuracyLet SPICE do what SPICE does best, and use fast logic simulation to handle RTL and gate-level circuitsVarious SPICE engines, + SystemVerilog, Verilog, Verilog-A, Verilog-AMS, or VHDLDirect kernel integration of SPICE and logic simulationSingle process, single executableMulti-level verificationUse abstracted models for system-level validationSlide7

Bottom LineMixed signal modeling and timing analysis CAN be doneEnables ultra-fast, ultra-small, ultra-low-power designsValuable verification technique to ensure working first silicon

Technical challenges

MS circuit timing analysis is not necessarily easy or exhaustive

Labor and compute resources can be expensive

Costs may really explode with increasing number of cornersContinuing progressModeling interface improvementsExpanding analysis support for analog-ish circuitsSlide8