1 schedule Significant submission delay encountered Time and jitter critical design very delicate Underestimate of finalizing simple things Simple things x large N large time Memory integration issue ID: 930639
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Slide1
Pico-second TDC Schedule & Production
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Slide2schedule
Significant submission delay encountered.
Time and jitter critical design very delicate
Underestimate of finalizing simple things: Simple things x large N = large time
Memory integration issueTrainee supposed to help with design, verification and test left at very unfortunate timeIntegration of custom blocksVerification took longer than expected (always does)Prototype submission: August 2018Initial bare die test: November - December 2018At CERN only, to verify chip is alivePackaging of 50-100 chips: Jan. – Feb. 2019Testing of packaged chips: March. – April 2019At CERN plus few selected users(Possible design corrections: May – June 2019)Production submission: July 2019Production chip test/verification: September - October 2019Chips available in quantity: October 2019
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Slide3PicoTDC
users and quantities(to be updated)
Project
Test
chipsFinal quantityCertainty0 - 10CBM103100?SuperFRS2100
?
Crispin
2??CAEN101000 - 2000?LHCb Torch21600?MPD/NA612150?IHEP BESIIII300?IHEP PET200?CMS-TOTEM PPS210?CMS timing layer?(10000)?ATLAS forward proton220?Mu2e100?Other ? (RD51, ?)??Total<50 5k – 20k
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Slide4Production scenarios, cost estimate
Masks, engineering run and packaging are dominating
costs: Prices in CHF/Euro/$
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2inch wafer (4kCHF) = 3.5k PicoTDCs per wafer ½ or ¼ if shared masks and process splitDedicated engineering. run: ~500k CHF, low metal layer countShared engineering run: ~250k CHF (could be less if several clients)Packaging + test: ~10 CHF per chipYield: ~2/3Dedicated engineering run:Eng run 5 wafers: 500k CHFChips: 5 x 3.5k 17k, ~10k workingPackaging/test: 17k x 10 170k, CHFCost per chip: 670k / 10k 67 CHF per chipPrice ~150 CHF per chip assuming half sold, for non commercialShared engineering runEng run 5 wafers: 250k CHFChips: 5 x 3.5/2 k 9k, ~6k working
Packaging/test: 9
k
x 10 90k CHFCost per chip: 340k / 6k 57 CHF per chipProduction run: Only after Engineering run25 wafers: 100k CHFChips: 25 x 3.5k 90k, 60k working, half if shared runPackaging/test: 90k x 5 450k CHFCost per chip: 550k / 60k 10 CHF per chip, double if shared runRealistic scenario: 10/6 k working chips produced, 5K assured to be soldNon commercial sales price: 150 CHF/E/$ per chip, Non commercial 2.3 CHF/E/$ per channelCommercial use: To be negotiated on case by case4