1 Design Plan - PowerPoint Presentation

Slide1

1

Design Plan of 2nd FEE prototype

Chih-Hsun Lin, Ming-Lee Chu, Chia-Yu Hsieh, Takahiro SawadaWen-Chen ChangInstitute of Physics, Academia Sinica, Taiwan

DC56 Bi-weekly MeetingJuly 10, 9-11am CDTSlide2

Outline1st FEM & Results of PerformanceNoise Test at IPAS & 2nd FEM Design PlanSchedule & ManpowerSummary2Slide3

1st FEM & Results of Performance3Slide4

Parameters of DC5/6ItemParameters

Active Area

X*Y=248*208 cm2

Plane

X,Y,U,V

Cell size

8 mm

Number of channels

(256+32)*8=2304

Gas mixture

Ar/C

2

H6/CF4 45/50/5Drift velocity of gas72 m/nsTime window75 nsPosition resolution200 mTiming resolution1 nsPile-up percent for 160(105) KHz event rate1.1(0.8) %Number of primary electrons~80Gas gain5*10^4Nominal charge injection2000000 e = 320 fCDiscriminator threshold 25000 e = 4 fC

4Slide5

FEE Components (1st FEE Design Plan)Front End Module (FEM):CMAD  preamplifier, shaper, discriminator TDC  FPGA-TDCData Collection Module (DCM): FPGA  Collect TDC data + Encoding data + Event buffer +CMAD controlOptical transceiver  deliver TDC data to GANDALFGANDALF : the interface module between DCM and readout buffer5Slide6

Schematic of FEE (1st FEE Design Plan)6Slide7

CMAD-DatasheetParametersCMAD

Number of Channel

8

Time resolution (Jitter)

< 1 ns (100 ps)

Shaper Peaking time

10-20 ns

Processing speed

> 5 MHz/chan

Linear dynamic range

0 – 900 fC

Noise level

0.63 fC (threshold 4 fC)Threshold level0 – 400 mV (800 mV)GainLow: 0.4 mV/fC – 1.2 mV/fC High: 1.6 mV/fC – 4.8 mV/fCGain resolution0.1 mV/fCInput signalSingle-endOutput signalLVDSDAC (gain, threshold, baseline)10 bitsPower consumption< 30 mW /per chan.7Slide8

CMAD (INFN, Torino)8Slide9

CMAD – Gain and Threshold SettingSet Digital Value [dig]Gain [mV/fC]Conversion factor [fC/dig]01.10.41

11.0

0.4520.9

0.5130.8

0.55

4

0.7

0.59

5

0.6

0.70

6

0.50.8670.401.1084.40.1094.00.11103.60.12113.20.14122.80.16132.40.18142.00.22151.60.28* Gain SettingLow GainHigh Gain* Threshold SettingMinimum thr.(pedestal)Maximum thr.0 digit650 digitAll the channels/chips are calibrated in order to have the pedestal positioned at 650 digit.9Slide10

FPGA-TDC: Lattice XP2250 MHz Clock, 1 ns Resolution10

1 CMAD + 1 TDC

4

CMAD + 1 TDCSlide11

Block diagram of FEM module11CMADDC wire

TDCMeasurement(1 ns accuracy)

0

90

270

360

Phase

Adjustment

PLL

38.88 MHz

~250 MHz

System Clock

Synch-resetFIFODACSetup FPGADCMSlide12

Xilinx Spartan-6 LXT (XC6SLX25T)12Slide13

Block diagram of DCM module13FEM FIFOSorting

Hit Buffer

Trigger

Matching

Trigger

Offset

Trigger Latency

TDC

Meas.

System Clock

Synch-reset

Trigger

Trigger WindowDividedBufferFIFOFPGAOpticalTransceiverGANDALFSlide14

160 MByte/s

14Slide15

15Slide16

Components (baseline for 2,560 channels)Preamplifier-DiscriminatorTDC

DCM Control Board

Gandalf

CMAD

FPGA-TDC

(LatticeXP2)

FPGA +

optical package

VME FPGA

8 Inputs/

8 Output

(8 channels)

8 Inputs/1 Output(8 channels)40 Inputs/1 Output(320 channels)8 optical inputs/outputs(2560 channels)300 piece(s)300 piece(s)8 piece(s)1 piece(s)INFN, Torino(READY)IPASIPASFreiburg(READY)16Slide17

FPGA TDCCMADWire input

Switching regulatorUSB

Daisy chain Daisy chain 1st FEM (used in DESY beam test)

CMADFPGA [ TDC + Collect TDC data + Encoding data + Event buffer +DAC control (DCM function)]USB – I/O

17Slide18

1st FEM Lab Test (FEM004) - Time Resolution

1-ns

time resolution is achieved for all channels.

18Slide19

1st FEM Lab Test (FEM004) – Noise Level

Noise (

fC

)

ch0 0.583



0.006

ch1 0.604



0.005

ch2 0.578

 0.004 Noise ( fC )ch6 0.681  0.009ch7 0.616  0.009* Results of noise level by threshold scan at gain= 4.4 mV/ fC.Noise ( fC )ch3 0.620  0.011ch4 0.610  0.004 ch5 0.608  0.00519Slide20

MWPC CMAD board ( Michela’s presentation)

1

st FEM prototype20

1st FEM Lab Test - NoiseThe noise level are

equivalent to the results of

MWPC CMAD

board

.

CMAD @ gain = 4.4 mV /

fC

CMAD @ gain = 4.4 mV /

fCSlide21

1st FEM Lab Test – Single-hit Rate21No event loss at 250k single-hit rate.Slide22

1st FEM Lab Test (FEM004) – TDC Linearity22TDC is determined by the 4 phase lock loops with 250 MHz clocks instead of delay-line.No visible non-linearity accumulation appears with more than 4 clock cycles.Slide23

1st FEM + PTA - Cosmic Ray Test @ UIUC23TDC spectrum for a set of DC prototype - PTA.drift windowCosmic Ray Test Set up

PTA

Trigger

scintillatorTracking DC 2,3

Trigger scintillator

Tracking DC 0,1,4

Small trigger

s

cintillatorSlide24

DESY Beam Test Result1st FEM + Proto. DC - PTA achieved a position resolution of ~ 200 um.24c

Position resolution

Efficiency

CMAD@ 4fC,1mV/fC,1.9kV,PTACMAD@ 4fC,1mV/fCSlide25

Noise level @ DESY Beam Test 25Noise could be under control but with lots of effort during the beam test.PTA was send to Taipei for the further investigation of sources of noise.Slide26

TDC Distribution @ DESY Beam Test26Trigger jiggeringor signal reflection?Slide27

Noise Test at IPAS & 2nd FEM Design Plan27Slide28

Noise Test of 1st FEM prototype @ Taipei (with PTA)Noise testSwitching regulator  We remove them from the board and apply DC low-power supply. The noise is reduced. We will replace it by the linear regulator in the 2nd FEM. USB  To be checked. Even though USB will not be used in the final FEM, we have to use it during the test.Shielding  Good Shielding of detector PCB and connector is very important. We will discuss it later.

FPGA

TDC

CMADWire input

Switching regulator

USB

Daisy chain

Daisy chain

1

st

FEM prototype

28

FPGA  To be checked. After this test we will decide whether the digital and analog parts should be separated. The pros and cons for the choices will be discussed later. Slide29

Noise Test of 1st FEM prototype @ Taipei (with PTA)29

4 fCCMAD @ gain = 1 mV/ fC

With HVCMAD @ gain = 1 mV/ fC , Without HV

* 1st FEM + PTA @ Taipei * 1st FEM + PTA @ DESY

Even though the EMI of 1

st

FEM is big, we can reduce noise below 4

fC

by good shielding and removing the switching regulator. We also get good result at Taipei.Slide30

2nd FEE Design PlanTo be Decided (1): Separation of Analog and Digital Parts.30Plan1A. Separate analog and digital partPlan 1B. Combine FPGA-TDC and CMAD on the same board StructureCMAD boards & Backplane & FPGA-TDC+ DCMFEM board (CMAD + FPGA-TDC ) + Daisy

chain + DCM boardProsPotentially less noisyMore mechanical flexibility

ConsWe have to be very careful of the mechanical structure between CMAD board and back plane. Potentially more noisyNote:

According to the test result in DESY beam test, the noise could be significantly reduced by good metal shielding. We are repeating the test in Taipei. If the noise could be indeed effectively reduced by this method, we prefer “Plan 1B” for the design.Slide31

31Slide32

32Slide33

2nd FEE Design PlanTo be Decided (2): Num. of channels per FEM moduleThe form factor of DC56 is similar to DC4. Therefore we will follow the geometry of ASD8 board which used for DC4. 33

ASD8 board

Plan 2A: 16-ch

per connector

 8 chips

per

board  64-ch per board

Plan

2B:

32-ch per connector

 16 chips

per

board  128-ch per boardIf it doesn’t affect the performance, we prefer 128ch per FEM board. The number of FEM boards will be reduced by half.Slide34

DC5/6 FEE Design (Plan 2A)Wires/per plane: 256+3236 CMADs5 FEMs (1 FEM = 8 CMADs )1 DCMno. of plane: 88 DCM

1 GANDALFspare modules: 10%

We will produce 50 FEMs and 10 DCMs.34Slide35

DC5/6 FEE Design (Plan 2B)Wires/per plane: 256+3236 CMADs3 FEMs (1 FEM = 16 CMADs )1 DCMno. of plane: 88

DCM 1 GANDALF

spare modules: 10%We will produce 30 FEMs and 10 DCMs.

35Slide36

2nd FEE Design PlanTo be Decided (3): ShieldingWe found that DC PCB is the main source of noise and thus the shielding of it is very important. Copper tape was used for this purpose but the conductivity is not good enough and difficult to handle. We have the following suggestions: Use multilayer PCB, with top and bottom covered by ground layer. (see PCB cross section view)Cover bottom PCB by metal shield onto PCB. (see PCB cross section view) making “via” which is the hole connecting the ground of top and bottom

PCBs. (see next slide)36Slide37

37detectordetector PCB

connector

1st FEM1st

FEMconnector

detector PCB

detectorSlide38

2nd FEE Design PlanTo be Decided (3): Shielding38Electronic board with via. This technique is used for reducing noise.

making via which is hole go though top and bottom ground on the PCB. The EM wave from outside will be destroyed before picked up by signal wire.Slide39

Schedule, manpower & summary39Slide40

Schedule (1)ActivityTimelineFEM

01/08/2012 – 31/03/2014

--Design/Layout/Fab (1st prototype)

01/08/2012 – 30/11/2012 (4 mons)

--Test

01/12/2012 – 31/03/2013 (4

mons

)

--Package of CMAD Chip

01/04/2013 – 30/04/2013 (1

mons

)

--Design/Layout/Fab (2nd prototype)01/07/2013 – 30/09/2013 (3 mons)--Test01/10/2013 – 31/12/2013 (2 mons)--Design/Layout/Fab (3rd prototype)01/01/2014 – 28/02/2014 (2 mons)--Test01/03/2014 – 31/03/2014 (1 mons)DCM01/07/2013 – 31/03/2014--Design/Layout /Fab (1st prototype)01/07/2013 – 30/09/2013 (3 mons)--Test01/10/2013 – 31/12/2013 (2 mons)--Design/Layout/Fab (2nd prototype)01/01/2014 – 28/02/2014 (2 mons)--Test01/03/2014 – 31/03/2014 (1 mons)40Slide41

Schedule (2)ActivityTimelineMass production

01/04/2014 – 31/05/2014 (2 mons)

Final test

01/06/2014 – 30/06/2014 (1 mons)

Delivery of FEE Components to CERN

01/07/2014 – 31/07/2014 (1

mon

)

On-site Installation of DC FEE

01/08/2014 – 30/09/2014 (2

mons

)

41Slide42

ManpowerProject manager: Wen-Chen Chang Engineer: Ming-Lee Chu (Analog part) Chih-Hsun Lin (Digital Part)Postdoc: Takahiro Sawada (system test and installation)Graduate student: Chia-Yu Hsieh (system test and installation)42Slide43

SummaryThe performance of 1st FEM prototype matches the specifications in term of noise level, TDC resolution and gain. We are surveying the noise of DC system (FEM+PTA) at IPAS. Some details of the design of 2nd FEM will be decided based on the outcomes.Things To Decided:Separation of Analog and Digital Parts.Connection scheme with DC5.Shielding and grounding scheme.LV power supply, power distribution, regulation and protection.The 2nd FEM and 1st DCM will be accomplished and tested before Dec. 2013.

We aim at accomplishing the installation of DC56 FEM by Oct. 2014.43Slide44

Back up44Slide45

Shielded Connector45The two-- and three--row connectors are available in 32, 64, and 96 positions.

Pitch is 2.54 mm.

Shielding

Male

Female

Slide46

AS8D46Slide47

DC PCB ShieldingBottom layer (Gnd)

Middle layer (signal)

Al frame / chamber

Al frame / chamber

G

G

S

3 rows connector

(Via)

(Via)

Metal hat

Side view

Bottom layer (Gnd)Via : go through top and bottom layer but avoiding signal wire47Slide48

DC PCB ShieldingTop view…….

connector

s

ignal

Via

48Slide49

FEM board

Optical link

49Slide50

DC PCB

e

xposed copper (Ground)exposed copper (Ground)

resistive plane

r

esistive plane

DC wire layout

Al frame / chamber

Al frame / chamber

50Slide51

2nd FEE design1 FEM = 8 CMADs = 64 ch1 DCM  4 FEMs  32 CMADs 1 DC  12 DCMs ( 3 lays or each side)2 DCs  24 DCMs 3

Gandalfs

439 mm

?

mm

DC input

** 16

ch

or 32

ch

CMAD

8 chFPGATDCFPGATDCCMAD 8 chCMAD 8 ch** Daisy chainor back plane Power, I/O** Daisy chainOr back planePower, I/O．．．．．．．．．** 8 or 16 CMADs．．．．．** 2 or 4 FPGA-TDC?51Slide52

CMAD Chip (Preamplifier/Comparator)ParametersCMAD

Number of Channel

8

Time resolution (Jitter)

< 1 ns (100 ps)

Shaper Peaking time

10-20 ns

Processing speed

> 5 MHz/chan

Linear dynamic range

0 – 900 fC

Noise level

0.63 fC (threshold 4 fC)Threshold level0 – 400 mV (800 mV)GainLow: 0.4 mV/fC – 1.2 mV/fC High: 1.6 mV/fC – 4.8 mV/fCGain resolution0.1 mV/fCInput signalSingle-endOutput signalLVDSDAC (gain, threshold)10 bitsPower consumption< 30 mW /per chan.52Slide53

DCM board (first prototype)Xilinx Spartan-6 LXT FPGA: serially controlling and performing data readout of 4*10 daisy-chained FEM cards.Maximum data size: 18bits*8chs*40cards=5760 bits. Transfer speed: 100 Mbps*10 chainsMaximum transfer time per event: 5.76s. On-board encoding and buffering scheme. A 256-unit circular memory buffer for recording TDC of hits in the past 6.6 s. (trigger latency? + longest drifting time 75nsec).One unit size = 25bits*8chs*40cards=8000 bits

, total memory size 8000*256=256kB.SFP Optical transceiver: Speed of transmission 3.2 Gbits/sec; < 2.5 sec for per trigger.

(Maximum trigger rate 100kHz 10 sec )53Slide54

GANDALF boards with optical mezzanine cardsIt receives and re-distributes the “Trigger and Control System” (TCS) signal into DCM boards. Different bits in the TCS word are used as triggers, RESET, begin of spill, end of spill and data enable. Upon receipt of the trigger, GANDALF will retrieve TDC data from the DCM boards via 8 channels of 3.2-Gbps optical link. Assuming 10% occupancy and 100k trigger rate, the data flow rate is 18bits/8*2560chs*0.1*100k = 57.6 MB/sec. These data will be further delivered to the Readout Buffer via the S-LINK with the data speed of 160 MB/sec.54