Arria 10 External Memory Interface Pin Guidelines - PowerPoint Presentation

Arria 10 External Memory Interface Pin Guidelines Quartus Prime Software v17.0

2Introduction Intel’s EMIF IP has many restrictions when it comes to pin placement This slide deck covers the following topics: I/O bank structure Adjacent/Contiguous banks Resource sharing Pin constraints EMIF placement For more information regarding EMIF pin placement, refer to the Planning Pin and FPGA Resources section in the External Memory Interface Handbook *EMIF = External Memory Interface

3Software Requirements Quartus Prime Software v17.0

Arria 10 Architecture 4 Arria 10 devices contain 2 I/O columns Each column is made up of banks/tiles A column can have up to 8 banks/tiles Each bank/tile is made up of 4 lanes Each lane contains 12 I/ Os Transceiver Block Transceiver Block Bank 3H Bank 3G Bank 3F Bank 3E Bank 3D Bank 3C Bank 3B Bank 3A Column 2 Column 3 Bank 2L Bank 2K Bank 2J Bank 2I Bank 2H Bank 2G Bank 2F Bank 2A I/O Lane 3 I/O Lane 2 I/O Center I/O Lane 1 I/O Lane 0 Bank

5General Pin Guidelines Pins for every EMIF must reside within a single I/O column For interfaces that span multiple banks (multi-bank interfaces): Banks need to be adjacent to one another Address/Command bank must be located in the center to minimize latency Unused pins can be used as GPIO All Address/Command and associated pins must reside within a single bank Address/Command and Data pins can share a bank Address/Command and Data pins cannot share an I/O lane Only an unused I/O lane in the Address/Command bank can be used to implement a Data group

6Adjacent/Contiguous Banks The following slides cover how to determine if banks are considered adjacent/contiguous To determine if banks are adjacent/contiguous: Refer to the following sections in the Arria 10 Core Fabric and General Purpose I/ Os Handbook : GPIO Banks, SERDES, and DPA Locations in Arria 10 DevicesI/O Banks Groups in Arria 10 DevicesBanks need to be in the same I/O column to be considered adjacent/contiguous

7Adjacent/Contiguous Banks Example: Arria 10 GX 320 Device Product Line GX 320 Package F27 F29 F34 F35 I/O Bank 2A 48 48 48 48 2J 48 48 48 48 2K 48 48 48 48 2L4848 4848 3A48 484848 3B‒ 4848 483C ‒ 4848 483D ‒2448 48Total 240360384384 2L 2J 2I 2A 3D 3C 3B 3A Transceiver Block LVDS I/O 3V I/O Refer to Figure 73 and Table 38 in the Arria 10 Core Fabric and General Purpose I/ Os Handbook Banks are adjacent/contiguous Note: Banks need to be in the same column to be considered adjacent/contiguous (i.e. Banks containing a 2 are not adjacent/contiguous to Banks containing a 3) Indicates these banks are not bonded out for specific package (i.e. Banks 3B, 3C, and 3D do not exist for F27 package) Indicates this bank is not fully bonded out for specific package (i.e. Bank 3D for package F29 only contains 24 I/Os)

8Non-Adjacent/Non-Contiguous Banks Example: Arria 10 GX 480 Device Product Line GX 480 Package F29 F34 F35 I/O Bank 2A 48 48 48 2I ‒ 12 12 2J 48 48 48 2K 48 48 48 2L48 4848 3A48 4848 3B4848 48 3C4848 48 3D 244848 3E ‒48 ‒ 3F ‒48 ‒ Total360 492 396 Refer to Figure 74 and Table 39 in the Arria 10 Core Fabric and General Purpose I/Os Handbook 2L 2K 2J 3F 3E 3D 3C Transceiver Block LVDS I/O 3V I/O 2I 2A 3B 3A Because Bank 2I is not bonded out for package F29, Banks 2A and 2J are not considered adjacent/contiguous Because Bank 2I is not fully bonded out for packages F34 and F35, Bank 2A is not considered adjacent/contiguous to Bank 2I Note: We know 2I is not adjacent to 2A (as opposed to 2J) because the image (left) shows a gap between 2A (always assume 2A is not adjacent in these kind of situations) Banks are adjacent/contiguous Banks are not adjacent/contiguous

9I/O Bank Sharing The following slides cover requirements for sharing I/O banks Memory interfaces can share a bank if they share the same: Protocol Clock (rate, frequency, PLL reference clock) Voltage (VCCIO, VREF) Memory interfaces cannot share: Any given lane in a bank Only one clock tree per lane Address/Command bank Interfaces cannot share the same controller or sequencer Unused pins can be used as GPIO

10I/O Bank Sharing Example: 2 DDR3 x16 Interfaces Controller 1 Data Addr/Cmd 1 Addr/Cmd 1 Addr/Cmd 1 Data 1 Data 1 Data 2 Controller 2 Data 2 Addr/Cmd 2 Addr/Cmd 2 Addr/Cmd 2 Unused (free for GPIO) Unused (free for GPIO) Data path Data path Address/Command Address/Command Bank N-1 Bank N Bank N+1

11Resource Sharing The following slides go into details regarding the sharing of resources across memory interfaces Certain resources are forced to be shared IOSSM & Hard Nios II for all interfaces in a column PLL/DLL do not need to be shared Each bank has one Resource Implication Hard Nios II Must sample all cal_done signals in a column to determine when calibration completes PLL reference clockInterfaces need to share the same protocol, rate, and frequency Core clock networkInterfaces need to share PLL reference clock (same restrictions as above) I/O bankInterfaces must share the same protocol, rate, and frequency OCT and RZQShould not be shared across interfaces (each interface has a dedicated pin)

12Nios II/IOAUX Sharing Interfaces placed in the same column will share the same Hard Nios II and IOAUX Hard Nios II calibrates each interface sequentially Must sample all cal_done signals in a column to determine when calibration completes RTL simulation behaves as if every interface has its own Hard Nios IIRefer to the Simulation Guidelines section for more details

13PLL Reference Clock Sharing Interfaces must share the same protocol, rate, and frequency Interfaces should be placed in the same column and in adjacent/contiguous banks If interfaces are not placed in adjacent/contiguous banks: Memory interfaces with a different PLL reference clock cannot be placed in-between the interfaces sharing the PLL reference clock Refer to slide 16 for more information PLL reference clock frequencies depends on selected memory frequency Arria 10 EMIF IP shows valid PLL reference clock frequencies It is recommended to use the default valueSelecting a slower frequency will impact performance

14Core Clock Network Sharing Synchronizes clocks in core domain between memory interfaces Fitter uses one core clock domain to synchronously access all interfaces in a column Interfaces must share PLL reference clock, protocol, rate, and frequency Interfaces in different columns cannot use this feature Interfaces should be placed in adjacent/contiguous banks User can share core clock networks through Master and Slave setting during IP generation Connect core_clks_master_out from the Master to all the core_clks_slave_in signals from the Slaves

Recommended Clock Sharing Example 15 EMIF 1 and EMIF 2 can share PLL reference clock and core clock network when: In adjacent/contiguous banks In the same column Share the same protocol, rate, and frequency Do not share the same protocol/rate/frequency Not in the same column EMIF 1 EMIF 2

Discouraged Clock Sharing Example 16 Not recommended when interfaces are not adjacent or span across the chip Cross-chip variation, clock tree span If clock sharing is still implemented: No memory interfaces with a different PLL reference clock can be placed in-between EMIF 1 and EMIF 2 EMIF 1 EMIF 2 Cross-chip variation and/or clock tree span Cross-chip variation and/or clock tree span Cross-chip variation and/or clock tree span Memory interfaces placed here must run at the same PLL reference clock frequency as EMIF 1 and EMIF 2

The following slides cover important information regarding pin placement 1 See slides 21 -22 for more details 17 Pin Constraints DDR3 DDR4 QDRIV RLDRAM3 Data Strobe All signals (DQS, DQ, DM) belonging to the same DQS group need to be constrained to the same I/O lane. All signals (DQS, DQ, DM, DBI) belonging to the same DQS group need to be constrained to the same I/O lane. All pins in a DQ group (DKA/DKB, QKA/QKB, DQA/DQB) need to be placed in the same I/O bank All pins in a DQ group (DK/QK, DQ, DM) need to be placed in the same I/O bank Data Related DQ pins need to be placed in the same I/O lane. Data groups and their respective clocks should be placed in the same bank to improve I/O timing. DM pins must be paired off with a DQ pin for proper functionality 1 Related DQ pins need to be placed in the same I/O lane. Data groups and their respective clocks should be placed in the same bank to improve I/O timing. DM/DBI pins must be paired off with a DQ pin for proper functionality1 Related DQ pins need to be placed in the same I/O lane (read signals should be grouped separately from write signals). Data groups and their respective clocks should be placed in the same bank to improve I/O timing Related DQ pins need to be placed in the same I/O lane (read signals should be grouped separately from write signals). Data groups and their respective clocks should be placed in the same bank to improve I/O timingAddress/Command Must be placed in predefined locations within an I/O bankMust be placed in predefined locations within an I/O bank Must be placed in predefined locations within an I/O bank Must be placed in predefined locations within an I/O bank

Address/Command Pin Placement 18 Pin indices for Address/Command pins can be found in the Scheme Table Example (right): Address/Command pins for x72 DDR4 single-rank UDIMM interface Pin # Port 47-36 ‒ 35 mem_bg[0] 34 mem_ba[1] 33 mem_ba[0] 32 mem_a [17] 31 mem_a[16] 30 mem_a[15] 29 mem_a[14] 28 mem_a[13] 27 mem_a[12] 26 oct_rzqin 25 pll_ref_clk (negative leg) 24 pll_ref_clk (positive leg) 23 mem_a[11] 22 mem_a[10] 21 mem_a[9] 20 mem_a[8] 19 mem_a[7] 18 mem_a[6] 17 mem_a[5] 16 mem_a[4] 15 mem_a[3] 14 mem_a[2] 13 mem_a[1] 12 mem_a[0] 11 mem_par[0] 10 ‒ 9 mem_ck_n[0] 8 mem_ck[0] 7 ‒ 6 mem_cke[0] 5 ‒ 4 mem_odt[0] 3 mem_act_n[0] 2 mem_cs_n[0] 1 mem_reset_n[0] 0 mem_bg[1]

19Address/Command Pin Placement Example: CK0 Locate the physical location for the CK0 pin Pin 8 according to Scheme Table Locate I/O bank desired for Address/Command and corresponding pin index Refer to Pin Table for specific device Assuming 10AS016 device, U19 package, and bank 2K for Address/Command: Pin C13 CK0 can be assigned to a specific pin or bank in the QSF file (located in project directory) set_location_assignment PIN_C13 –to CK0 or set_location_assignment IOBANK_2K –to CK0 Bank Number Index within I/O Bank U19 DQS for x4DQS for x8/x9 DQS for x16/x18DQS for x32/x362K9 B13DQSn14DQ7DQ3DQ1 2K8C13 DQS14DQ7DQ3DQ1 2K7A13 DQ14DQ7DQ3DQ1 2K6A12 DQ14DQ7 DQ3DQ1 I/O bank Pin index (0 – 47) Pin name

20Pin Placement PLL reference clock must be constrained to pins 24 and 25 in the Address/Command bank RZQ must be constrained to pin 26 in the Address/Command bank To constrain data groups and corresponding pins to appropriate lanes/banks: Constraining one DQS/DK/QK pin to a lane allows Fitter to place all DQ signals in respective DQS/DK/QK group Clock pins (CK0) must be constrained to pins 8 and 9 in the Address/Command bank Constraining the CK0 pin, one DQS/DK/QK pin per group, and the PLL reference clock pin will effectively lock the entire interface Fitter can rotate pins within a lane based on user pin assignments This method is recommended for constraining pins

Valid DM Pairing Example 21 G15 G16 E15 D15 E16 F16 H16 H15 F14 G14 H13 H12 x8 UDIMM I/O lane G15 G16 E15 D15 E16 F16 H16 H15 F14 G14 H13 H12 x8 UDIMM I/O lane DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 unused DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 unused DQ7 DQSp DQSn DQSp DQSn Bank Number Index within I/O Bank Dedicated Tx /Rx Channel U19 2K 47 LVDS2K_1n G15 2K 46 LVDS2K_1p G16 2K 45 LVDS2K_2n E15 2K 44 LVDS2K_2p D15 2K 43 LVDS2K_3n E16 2K 42 LVDS2K_3p F16 2K 41 LVDS2K_4n H16 2K 40 LVDS2K_4p H15 2K 39 LVDS2K_5n F14 2K 38 LVDS2K_5p G14 2K 37 LVDS2K_6n H13 2K 36 LVDS2K_6p H12 The following slides explain how to appropriately pair the DM pin with a DQ pin DM pins must be paired with a DQ pin for proper functionality Need to correspond to same LVDS pair (p and n) in the Pin Table Assuming 10AS016 device, U19 package, and bank 2K for Address/Command DM0 DM0

Invalid DM Pairing Example 22 G15 G16 E15 D15 E16 F16 H16 H15 F14 G14 H13 H12 x8 UDIMM I/O lane G15 G16 E15 D15 E16 F16 H16 H15 F14 G14 H13 H12 x8 UDIMM I/O lane DQ0 DQ1 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQSp DQSn DQSp DQSn In these cases, the DM pin is not paired with a DQ pin because they are not part of the same LVDS pair Pay attention to the Dedicated Tx /Rx Channel column in the pin tables DM0 DM0 DQ7 unused unused DQ2 Bank Number Index within I/O Bank Dedicated Tx /Rx Channel U19 2K 47 LVDS2K_1n G15 2K 46 LVDS2K_1p G16 2K 45 LVDS2K_2n E15 2K 44 LVDS2K_2p D15 2K 43 LVDS2K_3n E16 2K 42 LVDS2K_3p F16 2K 41 LVDS2K_4n H16 2K 40 LVDS2K_4p H15 2K 39 LVDS2K_5n F14 2K 38 LVDS2K_5p G14 2K 37 LVDS2K_6n H13 2K 36 LVDS2K_6p H12

23Pin Assignments Example: DDR3 x72 Interface Controller Data Bank 2L Bank 2K Bank 2J Data Data Data Data Addr / Cmd Addr / Cmd Addr / Cmd Data Data Data Data DDR3/DDR4 x72 w/ Hard Controller Requires 3 banks: 3 lanes for Addr / Cmd pins 9 lanes for Data pins Constraining pins CK0 to pin 8 in Bank 2K PLL reference clock to pins 24 and 25 in Bank 2K RZQ to pin 26 in Bank 2K DQS groups: DQS group 0 to lane 3 in Bank 2K DQS groups 1-4 to Bank 2J DQS groups 5-8 to Bank 2L Assuming 10AS016 device and U19 package

24Step 1: Determine Bank Requirements and Device The following slides explain the steps necessary for correct external memory interface placement Calculate the number of Address/Command and Data pins needed Determine the number of banks required Refer to table below for some examples: Refer to EMIF Device Selector for device selection based on EMIF requirements   Interface Width/Memory Configuration # of I/ Os # of I/O banks (non-sharing) # of I/O bank (sharing) DDR3 x8 w/o ECC 42 1 1 DDR3 x32 w/o ECC 75 2 1.75 DDR3 x32 w/ ECC (total width x48) 86 2 2 DDR3 x72 UDIMM single rank 130 3 2.75 DDR3 x72 UDIMM dual rank 13533 DDR3 x72 UDIMM quad rank1454 3.25DDR4 x16 w/o ECC5521.25 DDR4 x32 w/o ECC762 1.75DDR4 x72 UDIMM single rank13232.75 DDR4 x72 UDIMM dual rank139 33 DDR4 x72 UDIMM quad rank147 43.25

Step 2: Bank Selection 25 After calculating the number of banks required, you must select adjacent I/O banks to place a given memory interface Refer to slides 6-8 Bank consists of number and letter Number represents column in package Letter represents 48 pin I/O bank Example: If an interface requires 2 I/O banks Banks 2K and 2J are possible options assuming 10AS016 device, U19 package Bank Number Index within I/O Bank 2K 5 2K 4 2K 3 2K 2 2K 1 2K 0 2J 47 2J 46 2J 45 2J 44 2J 43 2J 42

Step 3: Bank Placement 26 Select middle bank for Address/Command pins Address/Command pins required 3 or 4 I/O lanes depending on the memory protocol and topology All Address/Command pins and associated pins must reside within a single bank Address/Command and Data pins can share a bank Address/Command and Data pins cannot share a lane Controller Data Bank 2L Bank 2K Bank 2J Data Data Data Data Addr / Cmd Addr / Cmd Addr / Cmd Data Data Data Data DDR3/DDR4 x72 interface (3 banks)

27Step 4: EMIF I/O Placement BluePrint is available for EMIF placement Requires synthesized design in Quartus Prime Pro Shows all legal positions for EMIF placement Drag-and-drop feature Can be accessed from Tools > BluePrint Platform DesignerFor more details on how to use BluePrint refer to this video

28Alternative Methods for EMIF Placement Manually constrain all interface signals to pin locations Plan interface placement in columns (I/O bank selection Use pin tables to find legal positions for each interface pin Assign pin locations in QSF Fast periphery placement Can be lengthy process (especially with multiple IPs) Manually constrain some interface signals and let Fitter handle the rest Requires constraining the CK0 pin, one DQS/DK/QK pin per group, and the PLL reference clock pin for each memory interface Fitter can rotate pins within a lane based on user pin assignments This method is recommended for constraining pins