PPT-Evaluation of Dynamic Branch Prediction Schemes in a MIPS P

Debajit B h attacharya Ali JavadiAbhari ELE 475 Final Project 9 th May 2012 Motivation Branch Prediction Simulation Setup amp Testing Methodology Dynamic Branch Prediction Single Bit Saturating Counter. Static Branch Prediction. Code around delayed branch. To reorder code around branches, need to predict branch statically when compile . Simplest scheme is to predict a branch as taken. Average misprediction = untaken branch frequency = 34% SPEC. (. iPhone. 3G). Jeff Brantley. Chris Gregg. Bill . Stitson. Processor Overview. Features. Designed for consumer and wireless products . RISC Processor with Harvard Architecture. Vector Floating Point coprocessor. CS 3220. Fall 2014. Hadi Esmaeilzadeh. hadi@cc.gatech.edu. . Georgia Institute of Technology. Some slides adopted from Prof. . Milos . Prvulovic. Control Hazards Revisited. Forwarding helps a lot with data hazards. Instruction Set Architecture. RISC Instruction Set Basics. All operations on data apply to data in registers and typically change the entire register. The only operations that affect memory are load and store operations. Saehoon Kim. §. , . Yuxiong He. *. ,. . Seung-won Hwang. §. , . Sameh Elnikety. *. , . Seungjin Choi. §. §. *. Web Search Engine . Requirement. 2. Queries. High quality + Low latency. This talk focuses on how to achieve low latency without compromising the quality. 5. Branch Prediction . (2.3) and . Scoreboarding. (A.7). 2. Why do we want to predict branches?. MIPS based pipeline – 1 instruction issued per cycle, branch hazard of 1 cycle.. Delayed branch. Modern processor and next generation – multiple instructions issued per cycle, more branch hazard cycles will incur.. Computer Architecture and Implementation. Montek Singh. Oct 10, 2016. Topic: . Instruction-Level . Parallelism - . I. (Dynamic Branch Prediction). Instruction-Level Parallelism. Exploit . parallelism . As we saw last week, dynamic instruction issue allows us to exploit as much parallelism as exists in instruction code. Our stalling situations are limited to finite resources, cache misses and branches. As we saw last week, dynamic instruction issue allows us to exploit as much parallelism as exists in instruction code. Our stalling situations are limited to finite resources, cache misses and branches. cycle. Structural hazards. A required resource is busy. Data hazard. Need to wait for previous instruction to complete its data read/write. Control hazard. Deciding on control action depends on previous instruction. Samira Khan University of Virginia Nov 13, 2017 COMPUTER ARCHITECTURE CS 6354 Branch Prediction I The content and concept of this course are adapted from CMU ECE 740 AGENDA Logistics Branch Prediction Saehoon Kim. §. , . Yuxiong He. *. ,. . Seung-won Hwang. §. , . Sameh Elnikety. *. , . Seungjin Choi. §. §. *. Web Search Engine . Requirement. 2. Queries. High quality + Low latency. This talk focuses on how to achieve low latency without compromising the quality. Draw a state machine for a 2 bit branch prediction scheme . Explain the impact on the compiler of branch delay. . Chapter 4 — The Processor — . 2. Control Hazards. Consider:. . add $t1, $zero, $zero # . Topics: branch predictors, out-of-order intro, register renaming. 2. 2-Bit Bimodal Prediction. For each branch, maintain a 2-bit saturating counter:. if the branch is taken: counter = min(3,counter+1).