Resource Estimations Jubin Mitra ERNO DAVID Outline Motivation Review of previous estimation Current Estimation Architecture Link wise Estimation Choice of Link Combination Glue Logic Underestimation ID: 784222
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Slide1
Status of CRU Firmware Resource Estimations
Jubin Mitra, ERNO DAVID
Slide2Outline
Motivation
Review of previous estimation
Current Estimation ArchitectureLink wise EstimationChoice of Link CombinationGlue Logic UnderestimationClock Resource Optimization
10-03-2016
Jubin MITRA
2
Slide3Motivation
CRU Firmware Design can broadly be
grouped
into 3 sections:CRU FIRMWARE = PERIPHERY LOGIC + GLUE LOGIC + DETECTOR SPECIFIC CORE LOGICBy PERIPHERY LOGIC it includes
Fixed Latency Interface GBT
10 G PON
DAQ Interface
PCIe
Gen3 GLUE Logic All internal bus signals used ,Routing Logic, CDC, etcDETECTOR SPECIFIC CORE LOGIC (Available Resources)= Arria 10 Total Logic Available – Periphery Logic Usage – Glue Logic Usage
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3
Slide4Review of previous estimation
This design shows the 1
st
Approximation of CRU firmware resource.GBT firmware was approximatedFIFO used for Detector Logic + Glue logic approximation10-03-2016
Jubin MITRA
4
Slide taken from Erno David and Tivadar Kiss presentation at 1
st
CRU WorkshopWeb-link: https://indico.cern.ch/event/395605/session/0/contribution/6/attachments/792607/1086460/CRU__Status_1stWS.pdf
Slide5Current Estimation
10-03-2016
Jubin MITRA
5
GBT
6 channel
Bonded
GBT
6 channelBonded
Pattern Gen
Pattern
Chk
Pattern Gen
Pattern
Chk
PCIe
Gen3
8 lanes
With DMA
PCIe
Gen3
8
lanes
With DMA
Pattern Gen
Pattern
Chk
Pattern Gen
Pattern
Chk
1 Channel
TTK
Pattern Gen
Pattern
Chk
Arria
10
(
PCIe
40)
Here 10G PON interface is approximated with Altera Transceiver Toolkit (TTK)
Design
NO GLUE LOGIC
Slide6Link wise
Estimation
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Jubin MITRA6
FIXED
Slide7TPC Sub-detector requirement
40 GBT Link (Wide-bus Coding at Standard Mode)
PCIe Gen3 16 channel lanes + DMA (Used Altera example design for approximation)1 TTK (dummy 10GPON)10-03-2016
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7
Combination 1 & 2 saves resources, however it is less optimized for fitter and power constraints
Combination 3 is more load balanced, however it need more resources
Slide840 GBT Links in Various Combinations
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8
As understood combination 2 saves on PLL resources.
Slide9Periphery Logic resource usage e
stimation for TPC requirement
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Slide10How our Resource Estimation may be underestimated ?
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10
Periphery Logic
Glue Logic
Detector Specific Logic
Slide11GLUE LOGIC NEEDED FOR CLOCK DOMAIN CROSSING ONLY
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11
GBT
LINK 1
GBT
LINK N
PCIe
Gen3
8 lanes
With DMA
PCIe
Gen3
8
lanes
With DMA
Arria
10
(
PCIe
40)
# Total No of FIFOs Needed = No of GBT Links + 2 (for
PCIe
)
# Depth and Width of FIFO depends on Clock Frequency crossing and Data Bus Width
CLOCK DOMAIN 1
(120 MHz/ 40 MHz)
CLOCK DOMAIN
2
(250 MHz)
DETERTOR
SPECIFIC
LOGIC
?
?
Slide12Conservation of Clock Resources
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12
GBT Rx LINK 1
40 BIT WORD @ 120 MHZ
120 BIT FRAME @ 40 MHZ
GEARBOX
PLL
For 40 links you will need 40 PLLs
Slide13Thank
You
&
Any Questioins
3/10/2016
CRU WEEKLY MEETING
13
Slide14BACK UP SLIDES
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14
Slide15Some Proposed Ideas over Weekly Meetings for Clock Optimization
IDEA 1 : Work Directly in 120 MHz domain
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15
IDEA 2 : USE FREQUENCY DIVIDER
(a) 50% Duty Cycle Conserved
(b) 50% Duty Cycle Not Conserved
Original design
Proposed design