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DELD EC  3 03  Digital System Design DELD EC  3 03  Digital System Design

DELD EC 3 03 Digital System Design - PowerPoint Presentation

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DELD EC 3 03 Digital System Design - PPT Presentation

wwwtechnocratsgroupeduin 2 SYLLABUS CONTENT ltSubject Namegt ltUnitNogt ltSessionNogt Registers and Counters Asynchronous and Synchronous counter counters with MOD numbers Down counter UPDOWN counter propagation delay in ripple counter programmable counter Pre s ID: 1029712

session counter subject unit counter session unit subject technocratsgroup www technocrats technology excellence bhopal institute shift serial parallel flip

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1. DELDEC 303 Digital System Design

2. www.technocratsgroup.edu.in2SYLLABUS CONTENT-<Subject Name> | <Unit-No> | <Session-No>Registers and Counters : Asynchronous and Synchronous counter, counters with MOD numbers, Down counter, UP/DOWN counter, propagation delay in ripple counter, programmable counter, Pre- settable counter, BCD counter, cascading, counter applications,Decoding in counter, Decoding glitches, Ring Counter, Johnson counter, Rotate left & Rotate right counter, Registers – Buffer, Shift left, shift right, shift left/Right registers, parallel in parallel out, serial in serial out, parallel in serial out, serial in parallel out registers. Technocrats Institute of Technology (Excellence), Bhopal

3. www.technocratsgroup.edu.in3<Subject Name> | <Unit-No> | <Session-No>Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such registers can be made to move within the registers and in/out of the registers by applying clock pulses. An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single bit of dataUse : Shift Registers are used for data storage or for the movement of data and are therefore commonly used inside calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format Technocrats Institute of Technology (Excellence), Bhopal

4. www.technocratsgroup.edu.in4<Subject Name> | <Unit-No> | <Session-No>Types of shift registers :Following are the four types of shift registers based on applying inputs and accessing of outputs. Serial In − Serial Out shift register. Serial In − Parallel Out shift register. Parallel In − Serial Out shift register. Parallel In − Parallel Out shift register. Technocrats Institute of Technology (Excellence), Bhopal

5. <Subject Name> | <Unit-No> | <Session-No>5 Technocrats Institute of Technology (Excellence), Bhopal

6. www.technocratsgroup.edu.in6<Subject Name> | <Unit-No> | <Session-No>serial in serial out shift register Serial In Serial Out (SISO) shift registers are a kind of shift registers where both data loading as well as data retrieval to/from the shift register occurs in serial-mode. Technocrats Institute of Technology (Excellence), Bhopal

7. www.technocratsgroup.edu.in7<Subject Name> | <Unit-No> | <Session-No>Serial In Serial Out (SISO) shift registers are a kind of shift registers where both data loading as well as data retrieval to/from the shift register occurs in serial-mode Technocrats Institute of Technology (Excellence), Bhopal

8. www.technocratsgroup.edu.in8<Subject Name> | <Unit-No> | <Session-No>.4-bit Serial-in to Parallel-out Shift Register:The serial-in parallel-out shift register is used to convert serial data into parallel data thus they are used in communication lines where demultiplexing of a data line into several parallel line is required In Serial In Parallel Out (SIPO) shift registers, the data is stored into the register serially while it is retrieved from it in parallel-fashion. Technocrats Institute of Technology (Excellence), Bhopal

9. www.technocratsgroup.edu.in9<Subject Name> | <Unit-No> | <Session-No> Technocrats Institute of Technology (Excellence), Bhopal

10. www.technocratsgroup.edu.in10<Subject Name> | <Unit-No> | <Session-No>Parallel-in to Serial-out (PISO)  -  the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control. Technocrats Institute of Technology (Excellence), Bhopal

11. www.technocratsgroup.edu.in11<Subject Name> | <Unit-No> | <Session-No>shift register parallel in parallel out Technocrats Institute of Technology (Excellence), Bhopal

12. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>12Counter is a sequential circuit. IA digital circuit which is used for a counting pulses is known as counter. Counter is the widest application of flip-flops. Counters  types, namely, (i)synchronousii)Asynchronous,  counter. These further can be subdivided into Up/Down Counter and such like.MOD CounterRing Counter, Johnson Counter, Technocrats Institute of Technology (Excellence), Bhopal

13. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>13Synchronous counters:Synchronous counters are easier to design than asynchronous counters. They are called synchronous counters because the clock input of the flip-flops. are all clocked together at the same time with the same clock signal. Due to this common clock pulse all output states switch or change simultaneously.Synchronous Counters are so called because the clock input of all the individual flip-flops within the counter are all clocked together at the same time by the same clock signal Technocrats Institute of Technology (Excellence), Bhopal

14. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>14SYNCHRONOUS COUNTER DESIGN STEPS/PROCEDURES. Determine the No. of FFs needed to support the counting sequence's. highest No.. 2n -1 ≥ Highest No. Build a State Transition Diagram. Build a State/Excitation Truth Table. Simplify expressions for FF inputs for each F/F on K-Maps. Technocrats Institute of Technology (Excellence), Bhopal

15. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>153 Bit SYNCHRONOUS COUNTER DESIGN:3 Bit can count 000 to 2n -1Count Sequence 000-111No. Of Flip Flop = n Taking T FF for designingConsider Excitation Table of TT FF Technocrats Institute of Technology (Excellence), Bhopal

16. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>16 Technocrats Institute of Technology (Excellence), Bhopal

17. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>17 Technocrats Institute of Technology (Excellence), Bhopal

18. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>18

19. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>194 Bit SYNCHRONOUS UP COUNTER DESIGN using J K FF :Total States= 16Count From 0000-1111 0-2n -1(0- -15)Highest No. 152 n >0r = N (no. of states 16) n-=4No. Of FF Required 4 Select Type o FF-JK FFMake Excitation Table Technocrats Institute of Technology (Excellence), Bhopal

20. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>20Analysis of 4 Bit SYNCHRONOUS UP COUNTER using J K FF : Technocrats Institute of Technology (Excellence), Bhopal

21. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>21 DESIGN OF MOD Counter using J K FF : MOD 5 Counter Technocrats Institute of Technology (Excellence), Bhopal

22. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>22QCQBQAQC+QB+QA+JcKcJBKBJAKA0000010x0x1x0010100x1xx10100110xx01X0111001x1xx1100000x10x1x101xxxxxxxxx110xxxxxxxxx111xxxxxxxxxCounter Table Technocrats Institute of Technology (Excellence), Bhopal

23. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>23 Technocrats Institute of Technology (Excellence), Bhopal

24. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>24 Technocrats Institute of Technology (Excellence), Bhopal

25. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>25 Technocrats Institute of Technology (Excellence), Bhopal

26. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>264 Bit Asynchronous UP CounterJ=k=1, Negative Edge Triggering and take output from Q, Remaining FF CLK from previous FF Q Technocrats Institute of Technology (Excellence), Bhopal

27. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>274 Bit Asynchronous UP Counter: J=k=1, Positive Edge Triggering and take output from Q, Remaining FF CLK from previous FF Q’ Technocrats Institute of Technology (Excellence), Bhopal

28. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>28Asynchronous UP and Down Counter: Technocrats Institute of Technology (Excellence), Bhopal

29. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>294 Bit ASYNCHRONOUS DOWN COUNTER DESIGN using J K FF : Technocrats Institute of Technology (Excellence), Bhopal

30. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>30BCD counters: It follow a sequence of ten states and count using BCD numbers from 0000 to 1001 and then returns to 0000 and repeats. Such a counter must have at least four flip-flops to represent each decimal digit, since a decimal digit is represented by a binary code with at least four bits giving a MOD-10 count.It is also known as Decade counter Technocrats Institute of Technology (Excellence), Bhopal

31. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>31ABCDA+B+C+D+JAKAJBKBJCKCJDKD000000010X0X0X1X000100100X0X1XX1001000110X0XX01X001101000X1XX1X1010001010XX00X1X010101100XX01XX1011001110XX0X01X011110001XX1X1X110001001X00X0X1X10010000X10X0XX1 Technocrats Institute of Technology (Excellence), Bhopal

32. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>32

33. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>33 Technocrats Institute of Technology (Excellence), Bhopal

34. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>34BCD counters: It follow a sequence of ten states and count using BCD numbers from 0000 to 1001 and then returns to 0000 and repeats. Such a counter must have at least four flip-flops to represent each decimal digit, since a decimal digit is represented by a binary code with at least four bits giving a MOD-10 count.It is also known as Decade counter Technocrats Institute of Technology (Excellence), Bhopal

35. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>35ABCDA+B+C+D+TATBTCTD000000010001000100100011001000110001001101000111010001010001010101100011011001110001011110001111100010010001100100001001 Technocrats Institute of Technology (Excellence), Bhopal

36. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>36 Technocrats Institute of Technology (Excellence), Bhopal

37. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>37 Technocrats Institute of Technology (Excellence), Bhopal

38. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>38 Ring Counter: It is synchronous counter, Circular Shift RegisterIt  is a type of counter composed of flip-flops connected into a shift register, with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure. Technocrats Institute of Technology (Excellence), Bhopal

39. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>39Johnson Counter:Johnson counter also known as creeping counter, is an example of synchronous counter. In Johnson counter, the complemented output of last flip flop is connected to input of first flip flop and to implement n-bit Johnson counter we require n flip-flop.It is one of the most important type of shift register counter. It provides 2k states and provide special timing sequence Technocrats Institute of Technology (Excellence), Bhopal

40. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>40Design synchronous counter using JK FF that follow the sequence000, 101, 110, 111, 011, 010, 000 Technocrats Institute of Technology (Excellence), Bhopal

41. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>41 Technocrats Institute of Technology (Excellence), Bhopal

42. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>42 Technocrats Institute of Technology (Excellence), Bhopal

43. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>43Glitches in Ripple Counter/Asynchronous CountersWhen designing asynchronous circuits it can happen that you get spikes (glitches) on the signal values • This is due to the presence of several signalling paths which have different delay times.There is a short delay between an input logic level changing and the corresponding output change.Glitches in digital circuits are unnecessary transitions due to varying path delays in the circuit. Balanced path delay techniques can be used for resolving differing path delays. To make path delays equal, buffer insertion is done on the faster paths. Balanced path delay will avoid glitches in the output.In Fig. spurious 0 is called a glitch. Technocrats Institute of Technology (Excellence), Bhopal

44. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>44Decoding Error in Ripple Counter/Asynchronous CountersDue to glitch occurs in asynchronous counters false 1 or 0 occurs that may result in decoding error.1/F= T=n+TP+TCLKWhere n= No. Of FFTP= Propagation Delay of One FFTclk =Clock timeDelay in timing of transition causes decoding error Technocrats Institute of Technology (Excellence), Bhopal

45. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>45Frequency Division:A Divide by N counter implies that it divides the input clock frequency by N (i.e N=2n ) If you cascade four flip-flops then, the output of every stage is divided by 2, if output is taken from the 4th flip-flop, then its output frequency is clock frequency divided by 16 (fclock/2^4). Technocrats Institute of Technology (Excellence), Bhopal

46. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>46 Technocrats Institute of Technology (Excellence), Bhopal

47. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>47In synchronous counter, all flip flops are triggered with same clock simultaneously.In asynchronous counter, different flip flops are triggered with different clock, not simultaneously.Synchronous Counter is faster than asynchronous counter in operation.Asynchronous Counter is slower than synchronous counter in operation.Synchronous Counter does not produce any decoding errors.Asynchronous Counter produces decoding error.Synchronous Counter is also called Parallel Counter.Asynchronous Counter is also called Serial Counter.In synchronous counter, propagation delay is less.In asynchronous counter, there is high propagation delay.Synchronous Counter examples are: Ring counter, Johnson counter.Asynchronous Counter examples are: Ripple UP counter, Ripple DOWN counter.Difference between Synchronous and Asynchronous Counter Technocrats Institute of Technology (Excellence), Bhopal

48. www.technocratsgroup.edu.inAny Query ? THANKYOU<Subject Name> | <Unit-No> | <Session-No>48 Technocrats Institute of Technology (Excellence), Bhopal

49. www.technocratsgroup.edu.in<Subject Name> | <Unit-No> | <Session-No>49JA=KB=JA=KB=JC=KC=JD=KD= Technocrats Institute of Technology (Excellence), Bhopal