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Presentations text content in 1 Advanced Digital Design

Slide1

1

Advanced Digital Design

Synthesis of Control Circuits

by A

.

Steininger

and J.

Lechner

Vienna University of Technology

Slide2

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

2

Outline

Control Circuits

Petri Nets & Signal Transition Graphs

Properties

Common PN/STG fragments

Synthesis of SI control circuits

State Encoding

Next-state functions

Implementation

Synthesis tool: Petrify

Slide3

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

3

Control Circuits

Control logic essential part of asynchronous circuitsHow to specify?How to implement?

Control ?

Latch

Comb.Logic

Latch

Comb

.

Logic

Latch

Req

Req

Req

Ack

Ack

Ack

Req

Ack

Req

Ack

Slide4

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

4

Petri Nets (PNs)

For modelling concurrent systems

Directed graph with nodes and arcs

Nodes: places, transitions

Places can be marked with tokens

Transition is enabled (allowed to fire) if all input places have tokens

When a transitions fires:

Token removed from all input places

Token added to each output place

Slide5

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

5

STGs

Restricted subclass of

petri

nets

PN transitions = signal transitions

Simple places omitted (places with a single input and a single output)

Places/arcs represent causal relationships between signal transitions

Marking represents circuit state

Slide6

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

6

PN/STG - Example

Muller C-

gate

Source:

[

Sparso

06]

Slide7

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

7

Properties of STGs I

Input free choice

Alternative transitions only controlled by mutually exclusive inputs

1-bounded

Max. one token per place

Liveness

STG is live

iff

from every reachable marking, every transition can eventually fire

Slide8

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

8

Typical PN/STG Fragments

Choice

Merge

Fork

Join

Slide9

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

9

PN/STG Fragments - Example

Source:

[

Sparso

06]

Slide10

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

10

Properties for STGs II

STGs

can

be

implemented

as

speed-independent

circuits

.

Requirements

:

Consistent state assignment

In any execution, any transition alternates between rising and falling

Persistency

Enabled signals will eventually fire, cannot be disabled by other transition

Complete state coding (CSC)

Different markings must represent different states

Slide11

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

11

Speed-Independence (SI)

Delay-model: speed-independenceArbitrary gate delays (bounded but unknown)Ideal zero-delay wires

Source:

[

Sparso

06]

Slide12

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

12

STG Synthesis

Specification

State graph

State Graph with CSC

Next-State functions

Decomposed functions

Gate netlist

Reachability

analysis

State

encoding

Boolean

minimization

Logic

decomposition

Technology

mapping

Slide13

Lecture "Advanced Digital Design"

© A.

Steininger & J. Lechner / TU Vienna

13

Specification

Source: [

Sparso

06]

Slide14

Lecture "Advanced Digital Design"

© A.

Steininger & J. Lechner / TU Vienna

14

State Graph

0000

0100

0110

0010

1

000

11

00

1110

1111

11

01

b+

c+

b-

c-

a+

b+

d+

c+

d-

a-

(

a,b,c,d

)

Slide15

Lecture "Advanced Digital Design"

© A.

Steininger & J. Lechner / TU Vienna

15

Excitation Regions for Output Signal c

0000

0100

0110

0010

1

000

11

00

1110

1111

11

01

b+

c+

b-

c-

a+

b+

d+

c+

d-

a-

QR1(c+)

ER1(c+)

ER2(c+)

ER1(c-)

Slide16

Lecture "Advanced Digital Design"

© A.

Steininger & J. Lechner / TU Vienna

16

Quiescent Regions for Output Signal c

0000

0100

0110

0010

1

000

11

00

1110

1111

11

01

b+

c+

b-

C-

a+

b+

d+

c+

d-

a-

QR1(c+)

QR1(c-)

Slide17

Lecture "Advanced Digital Design"

© A.

Steininger & J. Lechner / TU Vienna

17

Next-State FunctionsKV Diagram for c

cdab00011110000xxF01Rxx1110R11100xxx

0000

0100

0110

0010

1

000

11

00

1110

1111

11

01

b+

c+

b-

C-

a+

b+

d+

c+

d-

a-

QR1(c+)

ER1(c+)

ER2(c+)

ER1(c-)

QR1(c-)

Slide18

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

18

Atomic Complex Gate Implementation

cdab00011110000xxF01Rxx1110R11100xxx

c = d +

a‘b

+

bc

Attention:

Decomposition

into

simple

gates

can

introduce

hazards

!

Slide19

Lecture "Advanced Digital Design"

© A.

Steininger & J. Lechner / TU Vienna

19

State-holding Gates Implementation

Signals toggle between excitation and quiescent/stable regionsER(c+)  QR(c+)  ER(c-)  QR(c-) etc.Implementation with SR-latches, C-gates or generalized C-gates possible

Generalized

C-

element

Source: [

Sparso

06]

Slide20

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

20

State-holding GatesSet/Reset Functions

c =

Set

+ c

Reset

Set

Reset

= 0

Set

Function

:

must

contain

all

states

in ER(c+)

may

contain

states

in QR(c+)

may

contain

not

reachable

states

Reset

Function

:

must

contain

all

states

in ER(c-)

may

contain

states

in QR(c-)

may

contain

not

reachable

states

Slide21

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

21

State-holding Gates Implementation

cdab00011110000xxF01Rxx1110R11100xxx

Set

function

:

c-

set

= d +

a‘b

Slide22

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

22

State-holding Gates Implementation

cdab00011110000xxF01Rxx1110R11100xxx

Set

function:c-set = d + a‘b

Reset function:c-reset = b‘

Slide23

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

23

State-holding Gates Implementation

cdab00011110000xxF01Rxx1110R11100xxx

Set

function:c-set = d + a‘b

Reset function:c-reset = b‘

Slide24

Lecture "Advanced Digital Design"

© A.

Steininger

& J. Lechner / TU Vienna

24

State-holding GatesHazards

cdab00011110000xxF01Rxx1110R11100xxx

0000

0100

0110

0010

1

000

11

00

1110

1111

11

01

b+

c+

b-

c-

a+

b+

d+

c+

d-

a-

0

10

0

10

0

1

0

1 0

0

10

Slide25

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

25

State-holding GatesMonotonic Cover Constraint

A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint)

cdab00011110000xxF01Rxx1110R11100xxx

Hazardous

set

function

:

c-set = d + a‘b

Slide26

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

26

State-holding GatesMonotonic Cover Constraint

A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint)

cdab00011110000xxF01Rxx1110R11100xxx

Fixed

set

function

:

c-set = d + a‘bc‘

Slide27

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

27

ExampleVME Bus Controller

LDS+

LDTACK+

D+

DTACK-

DTACK+

DSr

-

D-

DSr

+

LDS-

LDTACK-

VME

Bus

Controller

DSr

DTACK

LDS

LDTACK

D

STG

of

Read Cycle

Slide28

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

28

VME Bus ControllerCSC Conflict

DSr

+

10000

00000

01000

10100

00100

01100

10110

00110

01110

11111

01111

10010

10110

10111

DSr

+

DSr

+

DTACK-

DTACK-

DTACK-

LDTACK-

LDTACK-

LDTACK-

LDS-

LDS-

LDS-

LDS+

LDTACK+

D+

DTACK+

DSr

-

D-

(

DSr

, DTACK, LDTACK, LDS, D)

Slide29

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

29

VME Bus ControllerCSC Conflict

LDS+

LDTACK+

D+

DTACK-

DTACK+

DSr

-

D-

DSr

+

LDS-

LDTACK-

10110

LDS+

LDTACK+

D+

DTACK-

DTACK+

DSr

-

D-

DSr

+

LDS-

LDTACK-

10110

Slide30

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

30

Resolving CSC ConflictConcurrency Reduction

Solution I: Remove conflict state by concurrency reduction

DSr

+

10000

00000

01000

10100

00100

01100

10110

00110

01110

11111

01111

10010

10110

10111

DSr

+

DSr

+

DTACK-

DTACK-

DTACK-

LDTACK-

LDTACK-

LDTACK-

LDS-

LDS-

LDS-

LDS+

LDTACK+

D+

DTACK+

DSr

-

D-

Slide31

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

31

Resolving CSC ConflictConcurrency Reduction

Solution I: Remove conflict state by concurrency reduction

DSr

+

10000

00000

01000

10100

00100

01100

00110

01110

11111

01111

10010

10110

10111

DSr

+

DTACK-

DTACK-

DTACK-

LDTACK-

LDTACK-

LDTACK-

LDS-

LDS-

LDS+

LDTACK+

D+

DTACK+

DSr

-

D-

Slide32

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

32

Resolving CSC ConflictConcurrency Reduction

Concurrency reduction reflected by adding an arc to the STG specification.Introduces timing assumption (LDS- before DSr+)

LDS+

LDTACK+

D+

DTACK-

DTACK+

DSr

-

D-

DSr

+

LDS-

LDTACK-

Slide33

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

33

Resolving CSC ConflictAdding State Signal

Solution II: Inserting an internal state signal to make conflict states unique

DSr

+

100000

000000

010000

101000

001000

011000

101100

001100

011100

111111

011111

100101

101101

101111

DSr

+

DSr

+

DTACK-

DTACK-

DTACK-

LDTACK-

LDTACK-

LDTACK-

LDS-

LDS-

LDS-

LDS+

LDTACK+

D+

DTACK+

DSr

-

D-

(

DSr

, DTACK, LDTACK, LDS, D,

CSC

)

100001

CSC+

011110

CSC-

Slide34

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

34

Petrify

Synthesis of

speed independent

control circuits from STG

specifcations

Simple text format for describing STGs

Petrify can solve CSC problem

Public domain tool

Developed at different universities

http://www.lsi.upc.edu/~jordicf/petrify/

Slide35

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

35

Petrify - Example

.model

cgate

.inputs a b

.outputs c

.graph

a+ c+

b+ c+

c+ a-

c+ b-

a- c-

b- c-

c- a+

c- b+

.marking { <c-, a+> <c-, b+> }

.end

Slide36

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

36

Petrify

Set of command-line tools

petrify: synthesis command

write_sg

: derives state graph

draw_astg

: draws STGs/state graphs

Different circuit implementations

Complex gates (-cg)

Generalized C-elements (-

gc

)

Specific target library (-tm)

Slide37

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

37

Summary

Control

logic

essential

part

of

asynchronous

circuits

PNs/STGs

convenient

for

modeling

control

circuits

STGs

need

to

fulfill

certain

properties

Input-

free

choice

, 1-bounded, CSC, etc.

Synthesis

from

STGs

to

SI

gate

implementations

possible

Tool

available

:

Petrify

Slide38


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