CSE 140 Components and Design Techniques for Digital Systems Spring 2019 CK Cheng Dept of Computer Science and Engineering University of California San Diego Outlines Class Schedule and Enrollment ID: 1031179
Download Presentation The PPT/PDF document "1 Lecture 1: Introduction to Digital Lo..." is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.
1. 1Lecture 1: Introduction to Digital Logic DesignCSE 140: Components and Design Techniques for Digital SystemsSpring 2019CK ChengDept. of Computer Science and EngineeringUniversity of California, San Diego
2. OutlinesClass Schedule and EnrollmentStaffInstructor, TAs, TutorsLogisticsWebsites, Textbooks, Grading PolicyMotivationMoore’s Law, Internet of Things, Quantum ComputingScopePosition among coursesCoverage2
3. Class Schedule and EnrollmentCSE140 A (enrollment 175, waitlist 19)Lecture: TR 5-620PM, PCYNH 106Discussion: F 11-1150AM, PCYNH 106Final: S 1130AM-130PM, 6/8/2019CSE140 B (enrollment 180, waitlist 9)Lecture: TR 2-320PM PCYNH 109Discussion: F 8-850PM, PCYNH 109Final: S 1130AM-130PM, 6/8/2019Waitlist: I welcome all students but have no control of the enrollmentNo discussion session on Friday 4/5/20193
4. Information about the InstructorInstructor: CK ChengEducation: Ph.D. in EECS UC BerkeleyIndustrial Experiences: Engineer of AMD, Mentor Graphics, Bellcore; Consultant for technology companiesEmail: ckcheng+140@ucsd.eduOffice: Room 2130 CSE BuildingOffice hours are posted on the course website12-1PM Monday; 10-1050AM ThursdayWebsiteshttp://cseweb.ucsd.edu/~kuanhttp://cseweb.ucsd.edu/classes/sp19/cse140-a4
5. Information about TAs and TutorsTAsWang, Ariel Xinyuan email:xiw193@ucsd.eduHsu, Po-Ya email:p8hsu@ucsd.eduAssare, Omid email:omid@ucsd.eduTutorsLin, Xiaokang, xil671@ucsd.edu Liu, Hanshuang hal286@ucsd.edu Luo, Weisi wel205@ucsd.edu Nichols, Andrew ainichol@ucsd.edu Ren, Alissa, alren@ucsd.edu Zhang, Shirley, shz199@ucsd.edu Zhu, Zhuowen, zhz402@ucsd.edu Office hours will be posted on the course website5
6. Logistics: Sites for the ClassClass website http://cseweb.ucsd.edu/classes/sp19/cse140-a/index.htmlIndex: Staff Contacts and Office HrsSyllabus Grading policy Class notes Assignment: Homework and zyBook ActivitiesExercises: Solutions and RubricsForum (Piazza): Online Discussion *make sure you have accessScore keepers: Gradescope, TritonEdzyBook: UCSDCSE140ChengSpring2019 6
7. 7Logistics: TextbooksRequired text:Online Textbook: Digital Design by F. VahidSign in or create an account at learn.zybooks.comEnter zyBook code UCSDCSE140ChengSpring2019Fill email address with domain @ucsd.eduFill section A or BClick Subscribe $50Reference texts (recommended and reserved in library)Digital Design, F. Vahid, 2010 (2nd Edition).Digital Design and Computer Architecture, D.M. Harris and S.L. Harris, Morgan Kaufmann, 2015 (ARM Edition).Digital Systems and Hardware/Firmware Algorithms, Milos D. Ercegovac and Tomas Lang.
8. Lecture: iCliker for Peer InstructionI will pose questions. You willSolo vote: Think for yourself and select answerDiscuss: Analyze problem in teams of threePractice analyzing, talking about challenging conceptsReach consensusClass wide discussion:Led by YOU (students) – tell us what you talked about in discussion that everyone should know.Many questions are open, i.e. no exact solutions.Emphasis is on reasoning and team discussionNo solution will be posted8
9. 9Grade on style, completeness and correctnesszyBook exercises: 10% (due Tuesday 2:00PM)iClicker: 0%Homework: 15% (grade based on a subset of problems)Midterm 1: 25% (T 4/23/19) Midterm 2: 25% (T 5/14/19) Final: 25% (1130AM-130PM, Saturday 6/8/19) Grading: The best of the followingThe threshold: A- >90% ; B- >80% of 100% scoreThe curve: (A+,A,A-) top 33±ε% of class; (B+,B,B-) second 33±ε%The bottom: C- above 45% of 100% score. Logistics: Grading
10. Logistic: grading componentszyBook: Interactive learning experienceNo excuse for delay (constrained by ZyBooks system)iClicker: Clarification of the concepts and team discussionHomework: Paper WorkGroup discussion is encouraged. However, we are required to write individually.Discount 10% loss of credit for each day after the deadline but no credit after the solution is posted.Metric: Posted solutions and rubrics, but not grading results10
11. Logistic: Midterms and FinalMidterms: (Another) Indication of how well we have absorbed the materialSamples will be posted for more practices.Solution and grading policy will be posted after the exam.Midterm 2 is not cumulative but requires a good command of the Midterm 1 content.Final: Two hours exam.Samples will be posted for more practices.Final is not cumulative but requires a good command of the whole class.11
12. Logistic: Class ExpectationLevel 1: Definitions (zyBook)Basic conceptsMotivationLevel 2: Concepts and Methods (Lecture and slides)Key ideasLevel 3: Hands on Practices (Homeworks)ExercisesLevel 4: Command of Materials (Samples of exams)Review12
13. Course Problems…CheatingWhat is cheating?Studying together in groups is not cheating but encouragedTurned-in work must be completely your own.Copying someone else’s solution on a HW or Exam is cheating Both “giver” and “receiver” are equally culpableWe will be better off to work on the problem alone during the exam.We have to address the issue once the cheating is reported by someone (e.g. TA, Tutor, Student, etc.).13
14. 14MotivationMicroelectronic technologies have revolutionized our world: cell phones, internet, rapid advances in medicine, etc.The semiconductor industry has grown from $21 billions in 1985, $335 billions in 2015, to $478 billions in 2018.
15. The Digital RevolutionWWIIIntegrated Circuit: Many digital operations on the same materialENIACMoore’s Law19651949Integrated CircuitExponential Growth of ComputationVacuum tubes(1.6 x 11.1 mm)Stored ProgramModel15
16. Building complex circuits16Transistor
17. 17Robert Noyce, 1927 - 1990Nicknamed “Mayor of Silicon Valley”Cofounded Fairchild Semiconductor in 1957Cofounded Intel in 1968Co-invented the integrated circuit
18. 18Gordon MooreCofounded Intel in 1968 with Robert Noyce. Moore’s Law: the number of transistors on a computer chip doubles every 1.5 years (observed in 1965)
19. Technology Trends: Moore’s LawSince 1975, transistor counts have doubled every two years.Moore’s law: wider applications: larger market: higher revenue: more R&D19
20. 20New TechnologiesNew materials and fabrication for devicesLow power devices Three dimensional integrated circuitsGrapheneNew architectureMachine learning, deep learningQuantum computingUnderstand the principles to explore the future
21. 21Artificial IntelligenceLogic and ReasoningBoolean SatisfiabilityProduct of sum clausesDiagnosisStates and SequencesSequential MachinesReachabilityControllabilityOne example of the applications and opportunities
22. 22ScopeThe purpose of this course is that we:Learn the principles of digital designLearn to systematically debug increasingly complex designs Design and build digital systemsLearn what’s under the hood of an electronic componentPrepare for the future technology revolution
23. Position among CSE CoursesBig idea: Coordination of many levels of abstractionCSE 140I/O systemProcessorCompilerOperatingSystem(Mac OSX)Application (ex: browser)Digital DesignCircuit DesignInstruction Set ArchitectureDatapath & Control TransistorsMemoryArchitectureSoftwareAssemblerDan GarciaCSE 120CSE 141CSE 131Algos: CSE 100, 101
24. 24Principle of AbstractionAbstraction: Hiding details when they are not importantCSE 30CSE 141CSE 140
25. 25fi(x,s)x1...xnCombinational Logic vs Sequential NetworkCombinational logic:yi = fi(x1,..,xn)CLKSequential Networks1. Memory 2. Time Steps (Clock)yit = fi (x1t,…,xnt, s1t, …,smt)sit+1 = gi(x1t,…,xnt, s1t,…,smt)fi(x)x1...xnfi(x)fi(x)x1...xnfi(x)si
26. 26Scope: Overall Picture of CS140Sequential machineConditionsControlMuxMemory FileALUMemory RegisterConditionsInputPointerCLK: Synchronizing ClockData Path SubsystemSelectControl SubsystemBSV: Design specification and modular design methodology
27. 27ScopeSubjectsBuilding BlocksTheoryCombinational LogicAND, OR, NOT, XORBoolean AlgebraSequential NetworkAND, OR, NOT, FFFinite State MachineStandard ModulesOperators, Interconnects, MemoryArithmetics, Universal LogicSystem DesignData Paths, Control PathsMethodologies
28. 28Combinational LogicBasics
29. What is a combinational circuit?29No memoryRealizes one or more functionsInputs and outputs can only have two discrete valuesPhysical domain (usually, voltages) (Ground 0V, Vdd 1V)Mathematical domain : Boolean variables (True, False)Differentiate between different representations:physical circuitschematic diagrammathematical expressions
30. Binary Digital LogicSimplest representation is “1” and “0” (base-2).Choose a physical quantity to represent “1” and “0”Usually voltage, but not always (e.g. current, resistance, magnetic polarization, quantum spin, …)Use a transistor to make the switch (operating as a digital instead of analog device) Two states – on / offSignals can be high voltage (“1”) or low voltage (“0”)30
31. Basic CMOSComplementary Metal Oxide SemiconductorInvented in the 1960’s, but took over in the 80’s“on” means low resistance, ”off” means high resistanceLogic “1” and Logic “0” values are arbitrarye.g. logic “1” == 1.0 V, logic “0” == 0.0 V 31NMOSPMOS”on” when gate is high ”on” when gate is low https://en.wikipedia.org/wiki/CMOS#/media/File:Cmos_impurity_profile.PNGddssggPlanar technologyFINFET technologyBy Irene Ringworm, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=3833512
32. Transistors as Switches32
33. The most basic CMOS gate - inverterWhen “inp” is “1”, then the nmos is on and the pmos is off – output will be ?When “inp” is “0”, then the nmos is off and the pmos is on – output will be ?33inpoutSchematicinout0110Truth TableinpoutEquationout = in’out =in
34. Basic Gates – (N)AND gate AND Y = A & B Y = AB34ABY000010100111NAND Y = (A & B)’ Y = (AB)’ABY001011101110ABYWhat kind of gate is this?ANDNANDInverterNone of the aboveBubble means Invert
35. Basic Gates – (N)OR gate OR Y = A + B Y = A | B35ABY000011101111NOR Y = (A + B)’ Y = (A | B)’ABY001010100110ABYBubble means InvertNOR is universal gateABY
36. <36>Boolean AlgebraA branch of algebra in which the values of the variables belong to a set B (e.g. {0, 1}), has two operations {+, .} that satisfy the following four sets of laws.Associative laws: (a+b)+c= a+(b+c), (a·b)·c =a·(b·c)Commutative laws: a+b=b+a, a·b=b·aDistributive laws: a+(b·c)=(a+b)·(a+c), a·(b+c)=a·b+a·cIdentity laws: a+0=a, a·1=aComplement laws: a+a’=1, a·a’=0(x’: the complement element of x)
37. DualitySwap (+, and complement all 0’s and 1’sIf we can prove a statement using laws of Boolean algebra true, then the duality of the statement is also true. 37Associative(a b) c = a (b c)(a b)c = a(bc)Commutativeab = baa+b = b+aDistributive*a(b+c) = ab + aca+(bc)=(a+b)(a+c)Identitya1 = aa+0 = aComplimentaa’ = 0a + a’ = 1AssociativeCommutativea+b = b+aDistributive*Identitya+0 = aComplimenta + a’ = 1Laws and their duals
38. Representations of combinational circuits:The Schematic38ABYWhat is the simplest combinational circuit that you know?
39. Representations of combinational circuitsTruth Table: Enumeration of all combinations39ABY=ABExample: ANDidABY0000101021003111
40. <40>Boolean AlgebraSimilar to regular algebra but defined on sets with only three basic ‘logic’ operations:Intersection: AND (2-input); Operator: ∙ ,&Union: OR (2-input); Operator: + ,|Complement: NOT ( 1-input); Operator: ‘ ,!“&, |, !” Symbols in BSV
41. Some Def’sComplement : variable with a “BAR” over it or ‘ after itA’Literal : variable or its complementImplicant: product of literalsABCImplicate: sum of literals(A+B+C)Minterm, maxterm (implicant or implicate that includes all the inputs)F(A,B,C,D): ABCD, (A+B+C+D)41
42. 42Two-input AND ( ∙ ) A B Y 0 0 0 0 1 0 1 0 0 1 1 1AND A B Y 0 0 0 0 1 1 1 0 1 1 1 1OR A Y 0 1 1 0NOT Boolean algebra and switching functionsFor an AND gate,0 at input blocks the other inputs and dominates the output1 at input passes signal AFor an OR gate,1 at input blocks the other inputs and dominates the output0 at input passes signal AA11A0AA1AA00Two-input OR (+ ) One-input NOT (Complement, ’ )
43. <43>Boolean AlgebraiClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+Y?F(X,Y)=0F(X,Y)=1F(X,Y)=2
44. <44>Boolean AlgebraiClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+X+Y?F(X,Y)=0F(X,Y)=1F(X,Y)=2
45. <45>Boolean AlgebraiClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+XY?F(X,Y)=0F(X,Y)=1F(X,Y)=2
46. <46>Boolean AlgebraiClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=(X+Y)Y?F(X,Y)=0F(X,Y)=1F(X,Y)=2
47. 47So, what is the point of representing gates as symbols and Boolean expressions?ab + cdabcdecdaby=e (ab+cd)Logic circuit vs. Boolean Algebra ExpressionSimplify the Boolean expression: Reduce the complexity of the circuitGiven the Boolean expression, we can draw the circuit it represents by cascading gates (and vice versa)
48. Switching Expression and Logic DiagramsSwitching Expression – Equations - # literals, # variables, # operatorsLiteral is a variable or its complement (e.g. a, a’)Variables (e.g. x)Operator (e.g. +, ·)Schematic / Logic Diagram - # of gates, # nets (wires), # of pinsGate (and, or, etc) – can be more than 2 inputs (e.g. 3 input AND gate)Net – wire that connects gatesPin - input or output of a gate.48
49. 49Associativity Laws (A+B) + C = A + (B+C) (AB)C = A(BC)CABABCCABABCLaws and Logic Diagrams
50. 50Distributive LawsA ∙(B+C) = A ∙ B + A ∙ CA+B ∙ C = (A+B) ∙(A+C)ABCACABABCACABLaws and Logic Diagrams
51. 51Switching Expression and LogicSchematic Diagram:5 primary inputs1 primary output4 components (gates)9 signal nets12 pinsa·b + c·dabcdec·da·by=e·(a·b+c·d)Boolean Algebra:5 variables1 expression4 operators 5 literals
52. 52Switching Expression and LogicSchematic Diagram:6 primary inputs1 primary output4 gates (3 ANDs, 1 OR)10 signal nets11 pinsNets are wires, Gates ->transistorsa·b + b’·cabb’cd’b’·ca·by= d’ ·e ·(a·b+b’·c)Switching Expression:5 variables1 expression4 operators (3 ANDs, 1 OR)6 literalsCost: #gates, #nets, #pinse
53. Example: f(a, b, c) = ab + a’c + a’b’53# variables# literals# gates
54. 54Which statement is not true in general?Schematic Diagram:5 primary inputs4 components (gates)9 signal nets12 pinsa·b + c·dabcdec·da·by=e·(a·b+c·d)Boolean Algebra: y=e·(a·b+c·d)5 literals4 operators#primary inputs = # literals#gates = # operators#nets = #variables + # operators#pins = # literals + 2 * #operators -1All of themBased on CK Cheng – CSE140 Spr18
55. Logic Diagram/Schematics 55https://commons.wikimedia.org/wiki/File:74181aluschematic.pngLogic circuit vs. Boolean Algebra ExpressionSimplify the Boolean expression: Reduce the complexity of the circuit
56. Next classDesigning Combinational circuits56