1 Advanced Digital Design

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1 Advanced Digital Design - Description

Description Methods. by A. . . Steininger. , J. . Lechner. and R. . Najvirt. Vienna University of Technology. Lecture "Advanced Digital Design" . © A. Steininger & J. Lechner / TU Vienna. 2. Outline. ID: 220901 Download Presentation

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1 Advanced Digital Design




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Presentations text content in 1 Advanced Digital Design

Slide1

1

Advanced Digital Design

Description Methods

by A

.

Steininger

, J.

Lechner

and R.

Najvirt

Vienna University of Technology

Slide2

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

2

Outline

Utilizing the potential of asynchronous circuits

Description methods

Standard HDL

STG, PRS, AFSM, TEL

Balsa, Haste, CHP

Slide3

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

3

Before the description comes the design

Once a circuit is

described

, optimization is limited to

what

is

in the description

The design of an average-case performing circuit is different than that of a worst-case timed one

This especially holds for the bundled data style but not only

Slide4

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

4

Average-Case DesignExample

A pipeline designed as if it was synchronous...

Clk

Slide5

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

5

Average-Case DesignExample

...now bundled data asynchronousHow much better is the performance?

Ctrl

Ctrl

Ctrl

Slide6

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

6

Average-Case DesignExample

What about now?

Ctrl

Ctrl

Ctrl

Slide7

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

7

The same now delay insensitivelyHow is the performance?

Average

-Case

Design

Example

Slide8

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

8

Average-Case DesignExample

What about now?

Slide9

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

9

Average-Case Design

In synchronous, concentrate on the worst path only

In asynchronous, create sets of paths with own worst path that are chosen from dynamically

Many optimization options

Somewhat similar to power optimization in synchronous circuits

One should know the capabilities of the tool in use

Slide10

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

10

Description of Async. Circuitswith Standard HDL

Description with standard HDL at low level (gate instantiations) naturally

possible

It

can also be used as a higher level design entry if the tool supports it

For example: Null Convention Logic

Timing requirements, if necessary, are difficult to express

Slide11

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

11

Null Convention Logic Design Entry

Circuit description in VHDL/

Verilog

with special coding style

Explicit coding of register components/control network

Data path can be described like for ordinary synchronous circuits

NCL library

Single-rail data

signals with data types fo

r multi-valued logic: 0, 1, N, U, X, Z, -

Overloaded o

perators

Hysteresis function for simulation

Slide12

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

12

Null Convention Logic Design Entry Example

library

ncl

;

use

ncl.ncl_logic.all,ncl.ack_logic.all

;

use

ncl.ncl_components.all

;

entity

enc_4_to_2

is

port

(

din

: in

ncl_logic_vector

(4

downto

1);

ack_in

,

reset

: in

ack_logic

;

ack_out

: out

ack_logic

;

dout

: out

ncl_logic_vector

(2

downto

1));

end enc_4_to_2;

Slide13

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

13

Null Convention Logic Design Entry Example

architecture

behave

of

enc_4_to_2

is

signal

b:

ncl_logic_vector

(2

downto

1);

begin

encode

:

process

(

din

)

begin

...

end

process

encode

;

ir1:

ncl_register_ss

generic

map

(

width

=> 2,

initial_value

=> -1,

stages

=> 1)

port

map

(

datain

=> d,

ki

=>

ack_in

,

rst

=>

reset

,

dataout

=>

dout

,

ko

=>

ack_out

);

end

behave

;

Slide14

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

14

Null Convention LogicSynthesis

RTL Synthesis

Transform VHDL/

Verilog

to 3NCL

netlist

Netlist

contains just AND & INV gates

Off-the-shelf synthesis tools

NULL values are treated as “don’t care”

Logic optimizations

Dual-rail expansion

3NCL

netlist

to 2NCL

netlist

DIMS implementation of AND & INV gates

Produces a delay-

insenstive

circuit

Logic optimizations

Slide15

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

15

Dual Rail NAND

DIMS

implementation

[

Ligthart

et al.,

2000]

Slide16

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

16

Null Convention Logic Technology Mapping

DIMS implementation inefficient

Techn

. mapping on threshold gates

Circuit functionality fully described by set function of DIMS implementation

DIMS smoothing: Derive

boolean

network representing set function

Threshold gates have specific set function

Perform logic optimization and map

boolean

network to available threshold gates

Slide17

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

17

Dual Rail NAND

DIMS

implementation

Set

function

[

Ligthart

et al.,

2000]

Slide18

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

18

Null Convention Logic Threshold Gates

Library of threshold gates by Theseusall unate functions with up to 4 inputs

Slide19

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

19

Specialized HDLs

Describing

async

. circuits with standard HDL can feel like hacking wrong tools to do the right thing

An overview of HDLs made for asynchronous:

Low level – STG, PRS, AFSM, TEL

High level – Balsa, Haste, CHP

Slide20

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

20

Signal Transition Graphs (STG)

Everybody should know them by now

© A. Steininger & J. Lechner / TU Vienna

Slide21

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

21

Production Rule Sets (PRS)

The representation for an intermediate step of the Martin synthesis (Caltech Asynchronous Synthesis Tools).Describes CMOS stacks directlyGeneralized C-Element as in previous lecture.

G

1

G

2

Slide22

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

22

Production Rule Sets (PRS)

G is called the guard

x is the assignment

x  x = 0

must hold by

definition (non-interference)

x  x = 1 implements combinational gate, if it can be 0 it is state holding

Guards must be stable (not change until output stable)

Slide23

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

23

Burst Mode FSM

NCL Half adder:

Slide24

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

24

Burst Mode FSM

Extension of fundamental mode AFSM

The

next-state function operates on input bursts, produces output bursts

No input burst can be a subset of an input burst of another transition going from the same state

Restricted fundamental mode

still

required – once a transition can happen, no input can change before the SM has stabilized

Slide25

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

25

Timed Event/Level Structures

Dependencies similar to STGsGuards similar to PRSsAdditionally, timing boundsNodes are events, edges are rules

Slide26

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

26

Timed Event/Level Structures

Instead of conflict places, conflicts are enlisted separatelyRules can be: marked enabled satisfied expired

Slide27

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

27

Communicating Hardware Processes

Design entry to Martin’s synthesis process developed at Caltech

Based on Hoare’s Communicating Sequential Processes formalism – like

many other parallel programming languages

Documentation

practically

unobtainable, yet used in many publications

Slide28

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner & R. Najvirt / TU Vienna

28

Communicating Hardware Processes

Main constructs:

Simple assignment:

v := true

or

v := false

Deterministic selection

[G1 -> S1 [] G2 -> S2] [G] is [G -> skip

]

Nondeterministic selection

[G1 -> S1 |

G2 ->

S2]

Repetition

*[G1 -> S1 [] G2 -> S2] *[S]

is

*[true -> S]

Sequencing and concurrent execution

S1; S2

and

S1, S2

Communication

C (synchronization)

C!x

(transmission)

C?x

(reception) #C (probe)

Slide29

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner & R. Najvirt / TU Vienna

29

Communicating Hardware Processes

Example – what does this do?

adide

= process(

X?int

(8),

Y?int

(8

),

Z!int

(8

))

u

:

int

(8)

*[

[ X ==>

X?u

;

Z!u

|

Y ==>

Y?u

;

Z!u

] ]

end

Slide30

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

30

Communicating Hardware Processes

Slide31

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

31

Balsa

Asynchronous high-level HDL & complete synthesis framework

Based on

Tangram

system by Philips

Open-Source

: Developed at University of Manchester

Syntax-directed compilation

1-to-1 mapping of language constructs to handshake circuit components

Allows experienced designer to easily envision the resulting

circuit but limits optimization potential

Slide32

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

32

BalsaHandshake Circuits

Approx. 40 handshake components

Connected over channels

Data path associated

Pure control channels (no data transferred)

Active ports initiate communication

Passive ports respond to request

Push channel

Data flow from active to passive port

Pull channel

Data flow from passive to active port

Slide33

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

33

Example: Handshake Components

Fetch () Transfers data upon requestCase (@)Conditional control flow element

Source: [Balsa Manual]

Slide34

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

34

The Balsa LanguageOverview

Similar to a typical imperative programming languageStrongly typedCircuit described with proceduresLike VHDL entity/architectureParameters represent in/out channelsProcedure call like component instantiation

procedure

foo

(input

i

: byte; output o : byte) is

--

Local

declarations

Begin

--

Implementation

end

Slide35

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

35

The Balsa LanguageTypes

Types based on bit vectors

Numeric types

Unsigned: Range [0, 2

n

-1]

S

igned:

Range [-2

n-1

, -2

n-1

-1]

Enumerations

Named numeric values

Records

Arrays

Slide36

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

36

The Balsa LanguageOperators

Standard logic/arithmetic operators

Control operators

Sequence operator (;)

Parallel composition (||)

Sync Command

Channel Operators

Read (->)

Write (<-)

Variable Assignment (:=)

Slide37

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

37

The Balsa LanguageConditional Execution

If statementsCase statements

-- Sequential evaluationif <Condition1> then <Command1>else if <Condition2> then <Command2> endend

-- Concurrent evaluationif <Condition1> then <Command1>| <Condition2> then <Command2>end

case

x+y

of

1 .. 4, 11 then o <- x

| 5 .. 10 then o <- y

else o <- z

end

Slide38

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

38

The Balsa LanguageLoops

Iterative execution (while loop)Structural iteration (for loop)Hardware instantiated for each iterationComparable to “for ... generate” in VHDL

-- Simple whilewhile <Condition> then <Command>end

-- Multiple guardswhile <Condition1> then <Command1>| <Condition2> then <Command2>| <Condition3> then <Command3>end

-- Sequential forfor ; i in 1 .. max_count then <Command>end

-- Parallel for

for ||

i

in 1 ..

max_count

then

<Command>

end

Slide39

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

39

Example:1-place Buffer

(-- buffer1.balsa:

Balsa program defining an 8 bit wide single

place buffer

--)

import

[

balsa.types.basic

]

procedure buffer1 (input

i

: byte; output o : byte) is

variable x :

byte

begin

loop

i -> x

-- Input

communication

;

--

Sequence

operator

o <- x

-- Output

communication

end

end

Slide40

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

40

Example:2-place Buffer

(-- buffer2.balsa:

a 2-place buffer using parallel composition --)

import

[

balsa.types.basic

]

import

[buffer1]

procedure buffer2 (input

i

: byte; output o : byte) is

channel

c :

byte

begin

buffer1 (i, c) ||

buffer1 (c, o)

end

Slide41

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

41

Example:Modulo-10 Counter

import

[

balsa.types.basic

]

type

C_size

is

nibble

constant

max_count

= 9

procedure count10(sync

aclk

; output count:

C_size

) is

variable

count_reg

:

C_size

variable

tmp

:

C_size

begin

loop

sync

aclk

;

if

count_reg

/=

max_count

then

tmp

:= (

count_reg

+ 1 as

C_size

)

else

tmp

:= 0

end ||

count

<-

count_reg

;

count_reg

:=

tmp

end

--

loop

end

--

begin

Slide42

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

42

Example:Modulo-10 Counter

Source: [Balsa Manual]

Slide43

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

43

Haste

Based on

Tangram

, very similar to Balsa in syntax

Design environment

TiDE

, distributed by Handshake Solutions, later Philips Semi.

Has additional constructs e.g. for level sensitive signals

Slide44

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

44

Haste

Slide45

Lecture "Advanced Digital Design"

© A. Steininger & J. Lechner / TU Vienna

45

Conclusion/Summary

Asynchronous

design

is

not

quite

the

same

as

synchronous

Specialize

d

description

methods

allow

for

EDA

tool

support

Still

active

field

of

research

many

methods

,

many

tools

Presented

description

methods

Allow

for

high-level

modeling

(RTL)

Proven

for

real-

life

circuits


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