PPT-Stash: Have Your Scratchpad and Cache it Too

Matthew D Sinclair et al UIUC Presenting by Sharmila Shridhar SoCs Need an Efficient Memory Hierarchy 2 Energyefficient memory hierarchy is essential Heterogeneous SoCs use . Message Passing Sharedmemory single copy of shared data in memory threads communicate by readingwriting to a shared location Messagepassing each thread has a copy of data in its own private memory that other threads cannot access threads communicate  Stefan . Schackow. Program Manager. Microsoft Corporation. PC41. What's the current state?. Why is it changing?. How are we changing it?. .NET Framework Caching. A great in-memory object cache in ASP.NET. Y. Sophia Shao, Sam Xi, . Gu-Yeon. Wei, David Brooks. Harvard University. More accelerators.. Out-of-Core. Accelerators. 2. [Die photo from . Chipworks. ]. [Accelerators annotated . by. Sophia . Shao @ Harvard]. Andrew Putnam, Susan Eggers. Dave Bennett, Eric Dellinger, Jeff Mason, . Henry Styles, . Prasanna. . Sundararajan. , Ralph Wittig. University of . Washington. -- CSE. Xilinx Research Labs. High-Performance Computing. OutlineoftalkCache-obliviousmodelCache-obliviousresultsCache-obliviouspriorityqueuesFunnelheap 6. Stashing. Sign in on the attendance sheet!. Git’stache. Scenario: you want to switch branches, but you have uncommitted changes. What if you don’t want to commit?. git. stash. Example use:. g. Y. Sophia Shao, Sam Xi, . Gu-Yeon. Wei, David Brooks. Harvard University. More accelerators.. Out-of-Core. Accelerators. 2. [Die photo from . Chipworks. ]. [Accelerators annotated . by. Sophia . Shao @ Harvard]. ECE . 751. Brian Coutinho. ,. David Schlais. ,. Gokul Ravi. &. Keshav . Mathur . Summary. Fact. : Accelerators gaining popularity - to improve performance and energy efficiency. Problem. : Accelerators with scratchpads require DMA calls to satisfy memory requests (among other overheads). Parallel. RAM:. Improved Efficiency. and . Generic Constructions. Binyi Chen. UCSB. . joint. . work. . with. Huijia. (Rachel). . Lin . . Stefano . Tessaro. File. . 5. . is. . important. Cloud Computing. With a superscalar, we might need to accommodate more than 1 per cycle. Typical server and . m. obile device. memory hierarchy. c. onfiguration with. b. asic sizes and. access times. PCs and laptops will. Direct-mapped caches. Set-associative caches. Impact of caches on performance. CS 105. Tour of the Black Holes of Computing. Cache Memories. C. ache memories . are small, fast SRAM-based memories managed automatically in hardware. March 28, 2017. Agenda. Review from last lecture. Cache access. Associativity. Replacement. Cache Performance. Cache Abstraction and Metrics. Cache hit rate = (# hits) / (# hits # misses) = (# hits) / (# accesses). TLC: A Tag-less Cache for reducing dynamic first level Cache Energy Presented by Rohit Reddy Takkala Introduction First level caches are performance critical and are therefore optimized for speed. Modern processors reduce the miss ratio by using set-associative caches and optimize latency by reading all ways in parallel with the TLB(Translation Lookaside Buffer) and tag lookup. ECE . 751. Brian Coutinho. ,. David Schlais. ,. Gokul Ravi. &. Keshav . Mathur . Summary. Fact. : Accelerators gaining popularity - to improve performance and energy efficiency. Problem. : Accelerators with scratchpads require DMA calls to satisfy memory requests (among other overheads).