on FD SOI 22nm Process Laurent Berti Outline Test structures overview Logic combinatorial Logic sequential Integrated clock gating ICG Ring oscillators Input output cells Bidirectional IOs amp LVDS ID: 1035682
Download Presentation The PPT/PDF document "DARE22 Test Vehicle Design" is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.
1. DARE22 Test Vehicle Design on FD SOI 22nm Process Laurent Berti
2. OutlineTest structures overviewLogic combinatorialLogic sequential Integrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMs 2
3. Test structures overview : What inside the TV ? which tests ?3StructureMeasurementsIrradiation testTIDSEESETSEUSELCombinatorial logicFunctional verification + SET cross section versus LET + SET duration + leakage vs TIDClock gating Functional verification + SET/SEU cross section versus LET + leakage vs TIDSequential logicFunctional verification + SEU cross section versus LET of standard and DICE FFP + leakage vs TIDRing oscillatorsFrequency (delay) versus TIDIOsCharacterization + ESD + performances versus TID + SET cross sectionAnalog IPCharacterization + performances versus TID + SEE cross sectionDPRAM (commercial)Functional verification vs TID + SEU cross section versus LET of the standard DPRAM + leakage vs TID
4. Sensitive AREA : RADEF facilityStandard beam flux 20k ions/(s.cm2)Max. fluence required: 1e7 ions/cm2 Min. strikes on active devices: 100SA = # events / fluence = 100 /1e7 = 1000 m2Beam duration: 500 s4
5. OutlineTest structures overviewCombinatorial logicSequential logicIntegrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMs Digital Test Interface5
6. Combinatorial logic: selected cells for THE radiation6CellsNumber of cells version to be testedNumber of devices per flavor to achieve SA = 1000 m2 Total area mm2 CLKINVD1/4/8/164811384/2816/1536/7040.155EXNORD11217920.041NAND2D1/2/43618432/11264/56320.203NAND3D1/2/43612288/7168/35840.195NOR2D1/2/43616384/9216/46080.176NOR3D1/2/43610240/5632/28160.175FILT60M127680.051TMV123840.024Total area + layout margin> 1.919
7. Combinatorial logic: Scan and SET test structures7Two configurations:Scan test (production test)Irradiation test (SET) 2 combiners CCELLs + delay cells (steps 10ps till 200ps, 20ps till 400ps and 50ps till 1ns)
8. Combinatorial logic8Outputs read and latch reset every 5ms (by the SPI)Probability of double events during 5ms: Probability to have at least 1 double event during 500s
9. OutlineTest structures overviewCombinatorial logicSequential logicIntegrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMs Digital Test Interface9
10. SEQUENTIAL logic: selected cells for THE radiation10CellsType FFPArea (mm2)SXDFFRLSLQD1 (SLVT, SVT, HVT, RVT) (20nm) DICE5.7914SXDFFRLSLQD1 (HVT) (28nm) DICE1.4478SDFFRLSLQD1 (12 flavors)standard0.4238Total area including layout margin11.5Due to the area limitation, only 5 flavors FF DICE implemented4 Vths for 20 nm + 1 Vth (HVT) for 28 nm (slowest flavor)SA can be calculated only for standard D-FFs. The DICE area is estimated by: active device area = 10*SA(standard DFF) Only 50% of the SA initially targeted has been implemented The irradiation time will be doubled
11. SEQUENTIAL logic: SEU DETECTION11SEU test configurations : pre-loaded data on a shift registerRad-hard clock buffering 6 configurations of tests : Data all 0, all 1 and checkerboard & Clk 0 and 1
12. OutlineTest structures overviewCombinatorial logicSequential logicIntegrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMsDigital Test Interface12
13. INTEGRATED Clock Gating: selected cells for THE radiation13CellsLETth(MeV.cm2/mg) Number of devices per flavor to achieve SA = 1000 m2 Area (mm2)ICGS3253840.079ICGS4402560.057ICGS5602560.060ICGD4non-hard11520.224Total area including margin> 0.6Integrated Clock Gating : mix between logic combinatorial and sequential ENTEGCLKSTATE QLatchCLK
14. INTEGRATED Clock Gating: SET/SEU detection14SETSETSET SETSETSETSETSETDetect SET/SEU and their propagations through the chain
15. OutlineTest structures overviewLogic combinatorialLogic sequential Integrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMs Digital Test Interface15
16. Ring Oscillators (1Ghz)1616 oscillators : 12 different flavors of INV (same as used for logic_comb delay) + 2 flavors with NAND/NOR gates Monitoring oscillation frequency (gate delay) and consumption versus TIDOutput signal frequency is divided by 128 (7.8125 MHz)
17. OutlineTest structures overviewLogic combinatorialLogic sequential Integrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMs Digital Test Interface17
18. Input/Output IO Cells18All IOs will be characterized with and without TID irradiation (leakage, output I/V curves, delay...):PUL/PDNSchmitt trigger threshold levelPOC signalLVDS standardHIF test (SET/SEL)BD IOsLVDS (RX/TX)ESD test: robustness of the IOs
19. Input/Output Cells : Bidirectional SET DETECTION19The SET detection at RX side is performed using 2 rad-hard latches, one for positive and the other for negative SET A SET filter is added at the latch output to remove latch SET
20. Input/Output Cells : LVDS SET tests20A loopback configuration between LVDS_RX and LVDS_TX is used during irradiation The SET detection is similar to the case of BD IOs : two hard-latches, and 2 RX for the TX discrimination
21. OutlineTest structures overviewLogic combinatorialLogic sequential Integrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Back Bias Generator (BBG) and TID sensorCommercial DPRAMs Digital Test Interface21
22. Analog Ips : IVREF1V822IVREF1V8 characterization with and without TID:Power-up and down consumptionsReferences voltage/current versus tuning codesReferences voltage/current values versus temperatureIVREF1V8 irradiation under HIFSET behavior (voltage variations)SEL robustness
23. IVREF1V8 : SET TEST CONFIGURATION23Two fast comparators with 2 rad-hard latches, connected to VREF Threshold detection fixed externally (pin TI_SETVREF)
24. Analog Ips : PLL24PLL characterizationPower-up and down consumptionsPLL frequency range: up to 3GHz (VCO frequency 2GHz-3GHz)Ultra low jitter (300 fs)PLL characterization under TIDPower-up and down consumptionsPLL frequency range vs TID dose (after the divider)PLL irradiation under HIFDetection of double edge SEL robustness
25. Analog Ips : PLL SET DETECTION252 ways to provide the input clock reference (to reduce the jitter)Specific output buffer for the jitter characterizationDivided PLL output signal (about 23MHz) to monitor SET
26. Analog Ips : Back Bias Generator (BBG) & TID sensor26Characterization with and without TIDPower-up and down consumptionsBody bias versus TIDHIF irradiation SET behavior : Don’t expect events, due to large filtering SEL robustness
27. OutlineTest structures overviewLogic combinatorialLogic sequential Integrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMs Digital Test Interface27
28. Commercial DPRAM (SYNOPSYS)28Characterization with and without TIDPower-up and down consumptionsTo investigate different memory cut sizesHIF irradiation To analyse the robustness of different DRAM configurations (different memory cut sizes) from SEU and MBU point of viewPre-load data, irradiate and after check data (static)Pre-load data, continuous reading and error counting during rradiation (dynamic)
29. OutlineTest structures overviewLogic combinatorialLogic sequential Integrated clock gating (ICG)Ring oscillators Input output cells (Bidirectional IOs & LVDS)Analog IPs IVREF1V8PLL Body Bias Generator (BBG) and TID sensorCommercial DPRAMs Digital Test Interface29
30. Digital Test Interface (DTI)30The DTI uses a SPI protocol and register bank, to control/read all the tested blocks This DTI has been designed to be rad-hard using DICE D-FF and a rad-hard clock-trees with triplicationTV top level view with DTIDTI top level view
31. Conclusion31Characterization TID and SEE:Combinatorial logicSequential logicClock gatingRing oscillatorIOsCommercial DPRAMIVREFPLLBack-bias generator & TID sensorPackaged dies expected early August 2022Radiation measurements before the end of this yearTV top layout (15 mm2)AcknowledgmentThe authors would like to thank the European Commission. This project (EFESOS) has been funded from the European Union’s Horizon 2020 research and innovation programme.
32. 32