and Overview Paulo Moreira On behalf of the GBT collaborations 20160308 httpcernchprojgbt PauloMoreiracernch 1 Outline The LpGBT amp VL Project Objectives The LpGBT ASIC LpGBT ID: 1046126
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1. The LpGBT ProjectStatus and OverviewPaulo MoreiraOn behalf of the GBT collaborations2016/03/08http://cern.ch/proj-gbtPaulo.Moreira@cern.ch1
2. OutlineThe LpGBT & VL+ Project ObjectivesThe LpGBT ASICLpGBT Block DiagramMain Features:Optical LinkE-LinksSlow ControlClock DistributionPower DissipationRadiation HardnessPackageThe ASIC and RadiationLpGBT Speed DomainsTID “Ion” DegradationRing / LC oscillator test PLLTID & SEUProject developmentsGBLD10GBLD10+VCSEL Driver ArraysLpGBT ASIC Development StatusLpGBT Project ScheduleGBT Chipset Statushttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch2
3. The LpGBT & VL+ Project ObjectivesDevelopment of Radiation Hard Optical LinksFor the Phase II Upgrades of the experiments (HL – LHC)Installation during the Long Shutdown 3 (Centred around ~2023)Main objectivesData rates:5 to 10 Gb/s for up links2.5 Gb/s for down linksEnvironmentTemperature: -35 to + 60 °CTotal Dose: 100 Mrad qualification (200 Mrad LpGBT chipset)Total Fluence: 2x1015 n/cm2 and 1x1015 hadrons/cm2Reduce the power consumption of the data transmission systemsReduce the footprint of the electronic and optoelectronic componentsOptoelectronic components (VL+):A low-profile packageMultiple channel and configurable:Number of channelsUnidirectional / bidirectionalhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch3No or small radiation dosesHigh radiation doses
4. LpGBT Block Diagramhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch45.12 / 10.24 Gb/s2.56 Gb/srefClk40MHzcdrOut [63:0]serIn [255:0]DEC&DSCRrxData[31:0]SCR&ENCrxEc[1:0]ePortTxeLinkOut[15:0]ecOutePortRxeLinkIn[27:0]ecIn40/…/1280 MHz40 MHzSCA(Reduced set)txData[159:0]txEc[3:0]PhaseShiftereClock[27:0]LpGBTControlSerDes40 MHz40 MHz40 / 80 / 160 / 320 / 640 /1280 MHzrxIc[1:0]txIc[1:0]40/…/1280 MHz40 MHz40/…/320 MHzcnt[x:0]psClk[3:0]I2C (x3)adcIn[7:0]pio[15:0]analogdatacontrolclockePortClk40/…/1280 MHzecClock
5. Main Features (1/…)“Optical” link:Down-link:2.56 Gb/s (64 – bit frame)Encoding: FEC12User bandwidth:IC (Internal Control (ASIC control)): 80 Mb/sEC (External Control (SCA e-Link)): 80 Mb/sD (Data): 1.28 Gb/sEye ScanBER Monitoring based on the FEC activityUp-link:User bandwidth @ 5.12 Gb/s (128 – bit frame):IC: 80 Mb/sEC: 80 Mb/sD:FEC12: 3.84 Gb/sFEC5: 4.48 Gb/sUser bandwidth @ 10.24 Gb/s (256 – bit frame)IC: 80 Mb/sEC: 80 Mb/sD:FEC12: 7.68 Gb/sFEC5: 8.96 Gb/sProgramable pre-emphasishttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch5Down-link bandwidth require by the experiments is typically small (no need for 5 or 10 Gb/s):Experiment controlTrigger informationEasier to achieve receiver SEU robustness at lower speeds!
6. Main Features (2/…)E-Links:Down-link:Bandwidths: 80/160/320 Mb/sNumber of links*: 16/8/4One EC channel @ 80 Mbit/sUp-Link:FEC5 @ 5.12 Gb/s:Data rate: 160 / 320 / 640 Mb/s# eLinks*: 28 / 14 / 7FEC5 @ 10.24 Gb/s: Bandwidth: 320 / 640 / 1280 Mb/s# eLinks*: 28 / 14 / 7FEC12 @ 5.12 Gb/s: Bandwidth: 160 / 320 / 640 Mb/s# eLinks*: 24 / 12 / 6FEC12 @ 10.24 Gb/s: Bandwidth: 320 / 640 / 1280 Mb/s# eLinks*: 24 / 12 / 6One EC channel @ 80 Mbit/sPhase alignment on a per channel basis:User programable phaseAutomatic phase trackinghttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch6* Excluding the EC channel
7. Main Features (3/…)LatencyBoth the RX and TX will have fixed and “deterministic” latencyeLink Line DriversProgramable:Driving current: 1, 2 and 4 mAReceiving end termination 100 W (external)Pre-emphasisDriver end termination (on/off - internal) (for back reflection cancelation)eLink Line ReceiversProgramable:100 W differential terminations (on/off)Auto bias for AC coupling (on/off)Line equalizationhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch7
8. Main Features (4/…)Slow Control:ASIC control:IC channel: 80 Mb/sI2C interfaceLpGBLD control:I2C masterExperiment control:Two I2C mastersProgrammable parallel port:16 x DIOEnvironmental parameters monitoring10-bit ADC:8 inputsTemperature:On chip: yesProgramable current source to drive an external temperature sensorhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch8
9. Main Features (5/…)Clock distribution:Phase/Frequency – 4 programmable clocks4 independentPhase resolution: 50 psFrequencies: 40 / 80 / 160 / 320 / 640 / 1280 MHzeLink Clocks:28 independentFixed phaseFrequency programable:40 / 80 / 160 / 320 / 640 / 1280 MHzClock jitter < 5 ps rmsPower dissipation:500 mW @ 5.12 Gb/s750 mW @ 10.24 Gb/sRadiation hardness:Total dose: 200 MradSEU robusthttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch9
10. Main Features (6/.)Package:BGAFine Pitch:0.5 mmPin count:289 (17 x 17)Size:Our wish would be:9 mm x 9 mm x 2 mmQuerying package providers for the availability of smaller packages.http://cern.ch/proj-gbtPaulo.Moreira@cern.ch10Preliminary # Ports# SignalsOptical Link Serial In12Serial Out12Power48eLinks eLink Down1632eLink Up2856eLink Clock2856eLink SC Down12eLink SC up12eLink SC Clock12Power918ASIC Control SDA - asic11SCL - asic11I2C - address44RST11Transceiver Mode44Lock Mode22Ref CLK12Ref CLK Select11Power12E-Fuse State overwrite11Ppulse11Power (x.xV)12Test Test In44Test Out44GBLD interface SDA - GBLD11SCL - GBLD11RST - GBLD11Phase-Shifter Clock48Power48I2C Master SDA - Master 1 & 222SCL - Master 1 & 222Power12SC - Control interface Parallel I/O1616DC/DC disable11Hard RST out22DC/DC power good33Power12ADC Voltage Inputs88Temp Sens Input11Digital Power48Total # Pins 276
11. LpGBT Speed Domainshttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch112.56 / 5.12 / 10.24 GHz clock domains1.28 GHz clock domain40 / 80 / 160 / 320 / 640 MHz clock domains
12. TID “Ion” Degradation1.28 GHzLogic cells will use enclosed devicesDevices non-minimum size:Required anyway for fast digitalSmall power penalty40 / 80 / 160 / 320 / 640 MHzSynergy with RD53Non-minimum size devicesOn R&D phasehttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch122.56 / 5.12 / 10.24 GHzCML logic will be usedAvoids the use of PMOS altogether It has a speed advantage It has a power penalty But, its use is restricted to a small fraction of the circuitry PMOSStrongly affectedL dependent:Longer is betterLmin required for fast digital logicW dependent:Wider is betterMinimum size:43% @ 100 MradEnclosed devices:The least affected5% @ 100 MradNon minimum sizeNMOSModerately affectedL dependent:Longer is betterLmin required for fast digital logicW dependent:Wider is betterMinimum size:10% @ 100 MradEnclosed devices:The least affected5% @ 100 MradNon minimum sizeD Ion [%]D Ion [%]
13. Ring / LC oscillator test PLL – TID & SEUhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch13Limit pointsRing oscillatorLC oscillatorTID: Ring OscillatorTID: LC OscillatorPaper submitted to NSREC 2015J. Prinzie et. al.TID: 9 Mrad/hour24 hours room Temp4, 24 hours @ 100 C24 hours room Temp24 hours @ 100 C2.5 GHz PLL (LC & Ring Oscillators)NMOS: L = 100 nm ; W = 2 um; nf = 32 x 4PMOS: L = 100 nm ; W = 3 um; nf = 32 x 4PMOS: L = 60 nm ; W = 3um; nf = 12NMOS: L = 180 nm; W = 3um; nf = 8 L = 180 nm; W = 3um; nf = 15
14. GBLD10Prototype:A low-power 10 Gb/s laser driver was prototyped in 130 nm CMOSMain Features:VCSEL driverLaser coupling:Differential AC with external componentsMinimum bit rate : 10 Gb/sProgramable pre-emphasisModulation current: 0-12 mADistributed amplifier structureQFN package, and ESD protectionArea: 2mm x 2mm (same as GLBD)Measurement results:Data rate: > 10 Gb/sPower dissipation: 86 mW (typical settings)Jitter: < 15 psInput Return Loss:< -14 dB (0 – 5 GHz)< -3 dB (10 GHz – 20GHz)Radiation hardness proved up to 500 MradNo annealing stephttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch14Electrical Eye Diagram @ 10 Gb/sSee: Zhang et all, TWEPP 2014, JINST 057P 1114
15. GBLD10+Prototype:A low-power / small-size 10 Gb/s laser driver was prototyped in 65 nm CMOSMain Features:VCSEL driverLaser coupling:Single-ended direct bondingMinimum bit rate : 10 Gb/sProgramable rise/fall pre-emphasisModulation current: 0-10 mABiasing current 0-12 mAQFN package, and ESD protectionArea: 1.75 mm x 0.4mmMeasurement results (electrical only):Data rate: 10 Gb/sPower dissipation: 31 mW (typical settings)Jitter: < 25 pshttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch15See: Zhang et all, TWEPP 2015Electrical Eye Diagram @ 10 Gb/s
16. VCSEL Driver ArraysLaser driver array being developed in Synergy with the VL+ projectSee talk: “Versatile link+ also in use-cases without GBT” presentation by Csaba Soos in this workshopTwo ASIC design projects ongoing by the departments of physics and engineering of the SMU university:4-way VCSEL driver arraySingle ended drivingInternal biasDesigned for direct bonding VCSEL arraysModulation and bias currents programable through I2CDesigns submitted for prototyping Feb 2016:Prototype testing foreseen for May 2016http://cern.ch/proj-gbtPaulo.Moreira@cern.ch16
17. LpGBT ASIC Development StatusHardwareRing and LC oscillator based PLL to test for SEU and TID (previous pages)10 Gb/s line driver:Programmable pre-emphasis (up to 10 dB)Fast digital library (90%)Enclosed layout for TID robustnessSubmission of a tests chip on the 23th of March (In collaboration with RD53)Phase-aligner DLL (80%)ePort Driver / Receiver (30%)RTLI2C SlaveI2C MasterIC linkScrambler/DescramblerePort RX/TX (80% complete)http://cern.ch/proj-gbtPaulo.Moreira@cern.ch17
18. LpGBT Project ScheduleLpGBTSpecification Q2 2015Full chip prototype out for manufacture Q4 2016Full chip prototype testing Q3 – Q4 2017Final Engineering run sent out Q2 2018First production batch available for users Q4 2019Completion of production Q4 2020http://cern.ch/proj-gbtPaulo.Moreira@cern.ch18
19. LpGBT CollaborationCERNSophie BarronRui FranciscoSzymon KulisPedro LeitãoRaul LesmaAlessandro MarchioroPaulo MoreiraDavid Porret Ken WyllieKU LeuvenBram FaesPaul LerouxJeffrey PrinzieSMUDatao GongPing GuiDi GuoDongxu YangJingbo YeZhiyao ZengTao Zhanghttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch19
20. GBT Chipset StatusGBTIAAll wafers produced26,000 chips diced and testedQuantities required for VTTRx available.GBLDAll the wafers produced94,000 chips packaged22,250 chips tested (remaining devices will be all tested during March)Quantities required for VTTRx and VTTX available MarchGBTXPre-series production completed (approx. 900 devices)Production testing to be done during AprilPre-production chips available for distribution in MayFirst-production lot (14,000 pieces):Launched April 2016Chips available for distribution, June 2016Production complete, September 2016GBT – SCASubmitted for prototype fabrication, November 2015Wafers expected end MarchIn house packaging April (general purpose ceramic package)ASIC evaluation testing, AprilSEU and TID qualification, MayWafer production, JuneWafers available, OctoberPackaged parts available in production quantities, Q1 2017http://cern.ch/proj-gbtPaulo.Moreira@cern.ch20