101-1 Under-Graduate Project - PowerPoint Presentation

Slide1

101-1 Under-Graduate Project Logic Design with Behavioral Models

Speaker:

Darcy Tsai

Adviser: Prof. An-

Yeu

Wu

Date: 2013/10/02Slide2

pp. 2OutlineOperationAssignment

Blocking and non-blocking

AppendixSlide3

pp. 3Various Abstraction of Verilog HDLGate level Verilog description of a full-adder

module fadder(cout, sum, a, b, cin);

// port declaration

output cout, sum;

input a, b, cin;

wire net1, net2, net3;

// Netlist description

xor U0(sum,a,b,cin);

and U1(net1, a, b);

and U2(net2, b, cin);

and U3(net3, cin, a);

or U4(cout, net1, net2, net3;

endmoduleSlide4

pp. 4Various Abstraction of Verilog HDLRTL level Verilog description of a full adder

module fadder(cout, sum, a, b, cin);

// port declaration

output cout, sum;

input a, b, cin;

wire cout, sum;

// RTL description

assign sum = a^b^cin;

assign cout = (a&b)|(b&cin)|(cin&a);

endmoduleSlide5

pp. 5Various Abstraction of Verilog HDLBehavioral level Verilog description of a full adder

module fadder(cout, sum, a, b, cin);

// port declaration

output cout, sum;

input a, b, cin;

reg cout, sum;

// behavior description

always @(a or b or cin)

begin

{cout,sum} = a + b + cin;

end

endmodule

+

a

b

cin

sum

coutSlide6

pp. 6OperatorsArithmetic Operators

examples:

A=4’b0011; B=4’b0100; // A and B are register vectors

D=6; E=4; //D and E are integers

A*B // 4’b1100

D/E // 1

A+B // 4’b0111

in1=4’b101x; in2=4’b1010;

sum=in1 + in2; // 4’bx

-

10 % 3 =

-1

// Take sign of the first operand

14 % -3 = 2Slide7

pp. 7Operators-example (arithmetic)Slide8

pp. 8OperatorBit-wise operators

~(101011)=010100

(010101)&(001100)=000100

(010101)|(001100)=011101

(010101)^(001100)=011001Slide9

pp. 9OperatorReduction operators (1-bit result)

&(10101010)=1

’

b0

|(10101010)=1

’

b1

&(10x0x0x)=1

’

b0

|(10x01010)=1

’

b1Slide10

pp. 10OperatorLogical operators

=== : determines whether two words match identically on a bit-by-bit basis, including bits that have values “x” and “z”Slide11

pp. 11OperatorShift operator

>>

logical shift right

<<

logical shift left

Slide12

pp. 12OperatorConditional Operator

Usage:

conditional_expression ? true_expression: false_expression;

The action of a conditional operator is similar to a multiplexerSlide13

pp. 13OperatorExamples of Conditional Operator

//model functionality of a tristate buffer

assign addr_bus = drive_enable ? addr_out : 36’bz;

//model functionality of a 2-to-1 multiplexer

assign out = control ? in1 : in0;

Conditional operations can be nested. Each

true_expression

or

false_expression

can itself be a conditional operation

assign out = s1 ? ( s0 ? i3 : i2 ) : ( s0 ? i1 : i0 );Slide14

pp. 14OperatorConditional Operator

module MUX4_1(out,i0,i1,i2,i3,sel);

output [3:0] out;

input [3:0] i0,i1,i2,i3;

input [1:0] sel;

assign out=(sel==2’b00)?i0:

(sel==2’b01)?i1:

(sel==2’b10)?i2:

(sel==2’b11)?i3:

4’bx;

endmoduleSlide15

pp. 15OperatorConcatenation and Replication OperatorSlide16

pp. 16Expression Bit Widths x ? y : z

Conditional

Bit width = max(width(y), width(z))

{x, …, y}

Concatenation

Bit width = width(x) + … + width(y)

{x{y, …, z}}

Replication

Bit width = x * (width(y) + … + width(z))

OperatorsSlide17

pp. 17Expressions with Operands

Containing x or z

Arithmetic

If any bit is x or z, result is all x’s.

Divide by 0 produces all x’s.

Relational

If any bit is x or z, result is x.

Logical

== and != If any bit is x or z, result is x.

===

and

!==

All bits including x and z values must match for equalitySlide18

pp. 18OutlineOperationAssignment

Blocking and non-blocking

AppendixSlide19

pp. 19AssignmentsAssignment: Drive value onto nets and registers

There are two basic forms of assignment

continuous assignment, which assigns values to nets

procedural assignment, which assigns values to registers

Basic formSlide20

pp. 20Assignments

Continuous assignment

Procedural assignment

module holiday_1(sat, sun, weekend);

input sat, sun; output weekend;

assign weekend = sat | sun; // outside a procedure

endmodule

module holiday_2(sat, sun, weekend);

input sat, sun; output weekend; reg weekend;

always #1 weekend = sat | sun; // inside a procedure

endmodule

module assignments

// continuous assignments go here

always begin

// procedural assignments go here

end

endmodule Slide21

pp. 21Continuous AssignmentDrive a value onto a wire, wand, wor, or triUse an explicit continuous assignment statement after declaration

Specify the continuous assignment statement in the same line as the declaration for a wire

Used for datapath descriptions

Used to model

combinational circuitsSlide22

pp. 22Continuous AssignmentsConvenient for logical or datapath specifications

Define bus widths

Continuous assignment: permanently sets the value of sum to be a+b+carryin

Recomputed when a, b, or carryin changes

wire [8:0] sum;

wire [7:0] a, b;

wire carryin;

assign sum = a + b + carryin;Slide23

pp. 23Continuous AssignmentsContinuous assignments provide a way to model combinational logicSlide24

pp. 24Continuous AssignmentsExamples of continuous Assignment

assign out = i1 & i2;

//

i1

and

i2

are nets

assign addr[15:0] =addr1[15:0] ^ addr2[15:0]

// Continuous assign for vector nets

addr

is a 16-bit vector net

//

addr1

and

addr2

are 16-bit vector registers

assign {cout, sum[3:0]}=a[3:0]+b[3:0]+cin;

//

LHS is a concatenation of a scalar net and vector net

Instead of declaring a net and then writing a continuous assignment on the net, Verilog provides a shortcut by which a continuous assignment can be placed on a net when it is declared.

wire a; --declareassign a=b&c; --assignwire a=b&c; --declare and assignSlide25

pp. 25Continuous AssignmentAvoid

logic loop

HDL Compiler and Design Compiler will automatically open up asynchronous logic loops

Without disabling the combinational feedback loop, the

s

tatic

t

iming

a

nalyzer

can

’

t resolve

ExampleSlide26

pp. 26Procedural AssignmentsProcedural assignments drive values or expressions onto registers (reg

,

integer

,

real

,

time

)

module adder32(sum,cout,a,b,ci);

output [31:0] sum;

output cout;

input [31:0] a,b;

input ci;

reg [31:0] sum;

reg cout;

always @(a or b or ci)

{carry,sum}=a+b+ci;

endmoduleSlide27

pp. 27Procedural Assignments

Inside an initial or always block:

Just like in C: RHS evaluated and assigned to LHS before next statement executes

RHS may contain wires and regs

Two possible sources for data

LHS must be a reg

Primitives or cont. assignment may set wire values

initial

begin

{cout, sum} = a + b + cin;

end

always

begin

{cout, sum} = a + b + cin;

endSlide28

pp. 28OutlineOperationAssignment

Blocking and non-blocking

AppendixSlide29

pp. 29Blocking vs. Non-Blocking (1/2)A sequence of nonblocking assignments don’t communicate

always @(posedge clk)

begin

a = 1;

b = a;

c = b;

end

Blocking assignment:

a = b = c = 1

always @(posedge clk)

begin

a <= 1;

b <= a;

c <= b;

end

Nonblocking assignment:

a = 1

b = old value of a

c = old value of bSlide30

pp. 30Blocking vs. Non-Blocking (2/2)RHS of nonblocking taken from flip-flops

RHS of blocking taken from wires

a = 1;

b = a;

c = b;

a <= 1;

b <= a;

c <= b;

1

a

b

c

“

”

a

b

c

1

“

”Slide31

Blocking or Non-Blocking?Blocking assignmentEvaluation and assignment are immediate

Nonblocking assignment

All assignment deferred until all right-hand sides have been evaluated (end of the virtual timestamp)

pp.

31Slide32

Blocking for Combinational LogicBoth synthesizable, but both correctly simulated?Non-blocking assignment do not reflect the intrinsic behavior of multi-stage combinational logic

pp.

32Slide33

Non-Blocking for Sequential LogicBlocking assignment do not reflect the intrinsic behavior of multi-stage sequential logic

pp.

33Slide34

Combinational & Sequential Logic Separation in Verilog CodeMixed Style

always@(posedge clk or negedge rst)

begin

if(~rst) begin

counter <= 4'd0;

out <= 8'd0;

finish <= 1'd0;

end

else begin

if(counter==4'd6) begin

counter <= 4'd0;

finish <= 1'd1;

end

else begin

counter <= counter+1'd1;

finish <= 1'd0;

end

out <= out + counter * in;

end

end

Separated Style

// combinational

always@(*) begin

if(counter==4'd6) begin

next_counter = 4'd0;

next_finish = 1'd1;

end

else begin

next_counter = counter+1'd1;

next_finish = 1'd0;

end

next_out = out + counter * in;

end

// sequential

always@(posedge clk or negedge rst)

begin

if(~rst) begin

counter <= 4'd0;

out <= 8'd0;

finish <= 1'd0;

end

else begin

counter <= next_counter;

finish <= next_finish;

out <= next_out;

end

end

Not recommended

Preferred

pp.

34Slide35

pp. 35Sequential Block

Sequential block may appear in an always or

initial statement

initial

begin

… imperative statements …

end

Runs when simulation starts

Terminates when control

reaches the end

(one time sequential activity flow)

Good for providing stimulus (testbenches); not synthesizable

always

begin

… imperative statements …

end

Runs when simulation starts

Restarts when control

reaches the end

(cycle sequential activity flow)

Good for modeling/specifying hardwareSlide36

pp. 36Sequential and Parallel BlocksThere are two types of blocks: sequential

blocks and

parallel

blocksSlide37

pp. 37Sequential and Parallel BlocksParallel blocks, specified by keywords fork and join, execute concurrentlySlide38

pp. 38Conditional StatementsIf and If-else statementsSlide39

pp. 39Conditional StatementsSlide40

pp. 40Multiway BranchingThe nested if-else-if

can become unwieldy if there are too many alternatives. A shortcut to achieve the same result is to use the

case

statementSlide41

pp. 41Multiway Branching4-to-1 Multiplexer with case

StatementSlide42

pp. 42Multiway BranchingThere are 2 variations of the case statement. They are denoted by keywords

casex

and

casez

casez

treats all

z

values in the case alternatives or the case expression as don’t cases. All bit positions with

z

can also represented by

?

In that position

casex

treats all

x

and

z

values in the case item or the case expresssion as don’t caresSlide43

pp. 43While LoopThe

while

loop executes until the

while

-expression becomes falseSlide44

pp. 44For LoopThe keyword

for

is used to specify this loop. The

for

loop contain 3 parts:

An initial condition

A check to see if the terminating condition is true

A procedural assignment to change value of the control variableSlide45

pp. 45Repeat LoopThe keyword

repeat

is used for this loop. The

repeat

construct executes the loop a

fixed

number of times.Slide46

pp. 46Forever LoopThe keyword

forever

is used to express the loop. The loop does not contain any expression and executes forever until the

$finish

task is encounteredSlide47

pp. 47Modeling A Flip-Flop With AlwaysVery basic: an edge-sensitive flip-flop

reg q;

always @(posedge clk)

q = d;

q = d assignment runs when clock rises: exactly the behavior you expect

Keywords:

posedge

for positive edge trigger

negedge

for negative edge triggerSlide48

pp. 48Timing ControlsEvent-Based Timing Control

Regular Event Control

Slide49

pp. 49Timing ControlsLevel-Sensitive Timing Control

always

wait (count_enable) #20 count = count +1 ;

// 1. If count_enable is logical 1, count=count+1

// after 20 time unit.

// 2. If count_enable stays at 1, count will be

// incremented every 20 time units

Slide50

pp. 50OutlineOperationAssignment

Blocking and non-blocking

AppendixSlide51

pp. 51Block DisableDisabling named blocks (example: comparator)Slide52

pp. 52TasksTask are declared with the keyword task

and

endtask

. It must be used if any one of the following conditions is true for the procedure

There are

delay

,

timing

, or

event control

constructs in the procedure

The procedure has

zero or more than one output arguments

The procedure has no input argumentSlide53

pp. 53Tasks exampleSlide54

pp. 54FunctionsFunctions are declared with the keywords function

and

endfunction

. Functions are used if all of the following conditions are true for the procedure

There are

no delay

,

timing

, or

event control

constructs in the procedure

The procedure

returns a single value

There is

at least one input argument

There are some peculiarities of functions. When a function is declared, a register with name (name of function) is declared implicitly inside.

Functions

cannot invoke other tasks

. They can only invoke other functionsSlide55

pp. 55Functions exampleSlide56

pp. 56Differences Between Tasks and Functions

Tasks and Functions