PPT-On Avoiding Spare Aborts in Transactional Memory

Idit Keidar and Dmitri Perelman Technion 1 SPAA 2009 Transactional Memory Background The emergence of multicore architectures Conventional locking Transactional Memory is a new synchronization abstraction . tumde Abstract So far transactional memoryalthough a promising techniquesuffered from the absence of an ef64257cient hardware implementation The upcoming Haswell microarchitecture from Intel introduces hardware transactional memory HTM in mainstream of Electrical Engineering Technion Haifa 32000 Israel idisheetechnionacil dima39txtechnionacil Abstract This paper takes a step toward developing a theory for understanding aborts in transactional memory systems TMs Existing TMs may abort many trans edu Binoy Ravindran Virginia Tech binoyvtedu Roberto Palmieri Virginia Tech robertopvtedu ABSTRACT Existing distributed transactional system execution model based on globallyconsistent contention management poli cies may abort many transactions that Gokarna. Sharma. Costas Busch. Louisiana State University, USA. WTTM 2010 - 2nd Workshop on the Theory of Transactional Memory. 1. TexPoint fonts used in EMF. . Read the TexPoint manual before you delete this box.: . Idit. . Keidar. and Dmitri Perelman. Technion. 1. SPAA 2009. Transactional Memory – Background. The emergence of multi-core architectures… . Conventional locking… . Transactional Memory is a new synchronization abstraction… . Memory. Supporting Large Transactions. Anvesh. . Komuravelli. Abe Othman. Kanat. . Tangwongsan. Hardware-based. . Concurrent Programs. obj.x. = 7;. find_primes. ();. // intrusion test. if (. obj.x. Rajwar. , R., . Herlihy. , M., and Lai, K. 2005. presented by . VasilyVolkov. , 04/30/08. Motivation. Transactional Memory is good. Never deadlocks. Makes concurrent programming easier. But requires programmer to be aware of. Patrick Santos (4465359). 1. Agenda. What is transactional memory (TM)?. Example transactions. Deadlocks and Cache Coherence. Types of TM. Implementations . & proposals . in industry. Sun / Oracle. 1. The University of Texas at Austin. The University of Texas at Austin. Ali Shafiee. , A. . Gundu. , M. . Shevgoor. , R. . Balasubramonian. and M. . Tiwari. Shared Memory Controller. Core1. $. MC. Core0. Maurice Herlihy (DEC), J. Eliot & B. Moss (UMass). Presenter: Mariano Diaz. CS 5204 – Fall, 2009. Part 1: Concepts and Hardware-based Approaches. Introduction. What’s a transaction?. Transaction: a finite sequence of machine instructions, executed by a single process, that satisfies the following:. Prof. Smruti R. Sarangi. IIT Delhi. Outline. Multicore Processors. Parallel Programming Pardigms. Transactional Memory: Basics. Software Transactional Memory(STM). Hardware Transactional Memory. Multicores in the last Five Years. Prof. Smruti R. Sarangi. IIT Delhi. Outline. Multicore Processors. Parallel Programming Pardigms. Transactional Memory: Basics. Software Transactional Memory(STM). Hardware Transactional Memory. Multicores in the last Five Years. Idit. . Keidar. and Dmitri Perelman. Technion. 1. SPAA 2009. Transactional Memory – Background. The emergence of multi-core architectures… . Conventional locking… . Transactional Memory is a new synchronization abstraction… . Alvaro Moreira & Luigi Carro. Instituto de Informática – UFRGS . Brasil. 1. Outline – Part III. Work . done at UFRGS on . detection/correction . of . Control Flow Errors (CFEs) with LLVM. Similarities and differences with Security.