1 The University of Texas at Austin The University of Texas at Austin Ali Shafiee A Gundu M Shevgoor R Balasubramonian and M Tiwari Shared Memory Controller Core1 MC Core0 ID: 463790
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Slide1
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies
1
The University of Texas at Austin
The University of Texas at Austin
Ali Shafiee
, A.
Gundu
, M.
Shevgoor
, R.
Balasubramonian
and M.
TiwariSlide2
Shared Memory Controller
Core1$
MC
Core0
$
2
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide3
3
Core 0
$
MC
3rd party
software
Core 1
$
Core 0: load changed
Core 1: access latency changed
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide4
Fixed Service
RD
D
M
WR
DM
WR
RD
time
Slot
L
Quantum Q= 4xL
Goal: Minimize L
Such thatL is enough to transfer one read or one writeWhile Satisfying cmd-to-cmd min
time gapsData Placement relaxes time gaps smart data placement shorter L4
0
123CPUAvoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide5
Mechanics of Memory
Data
Bus
CA
Bus
Rank 0
Rank 1
Bank
Bank
Bank
Bank
Memory Access
= ACT+ CAS
ACT
CAS
5
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide6
Memory Constraints6
ACT
CAS
ACT
0
0
CAS
0
6
Rank(A)
Rank(B)
ACT
CAS
ACT
5
0
CAS
0
4
Rank(0) Rank(0)
Bank(A)
B
ank(B)
ACT
CAS
ACT
5
11
CAS
28
4
Rank(0) Rank(0)
Bank(A)
Bank(A)
1
2
1
2
1
2
t
BURST
t
RTRS
t
BURST
t
RRD
t
FAW
t
CCD
t
RCD
t
RAS
t
RC
t
RP
t
RTP
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide7
Memory PartitioningRank-Part: Rank PartitioningBank-Part: Bank PartitioningNo-Part: No Partitioning
Core 0
Core 1
Core 2
Core 0
Core 1
Core 2
Core 3
7
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide8
Formulating The Problem
RD
RD
WR
RD
RD
WR
time
Data Bus
0L
1
L
2
L
3L
4L
5L
timeCA BusACTCASTRCD
T
CAS
CAS
ACT
T
RCD
T
CWD
KL-T
CAS
KL-(T
CAS
+T
RCD
)
KL-T
CWD
KL-(T
CWD
+T
RCD
)
Fixed Periodic
Transfer
8
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide9
Rank
PartitioningEnough Time to TransferNo Collision on CA Bus
L ≥TBURST+TRTRS L ≥ 6
CAS(RD) ≠ CAS (WR)KL-11 ≠ K’L-5
Rank-Part L=7
Bank-Part
L=15No-Part
L=439(K-K’)L ≠6 L≠6
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide10
Bank-Part with Re-ordering
R
W
RR
W
R
WW
L=15
R
W
R
R
W
R
W
W
L=6
L=15Return to CPUen masseQ=120Q=63
10
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide11
No-Part with Triple-Alternation
0
1
23
4
5
6
7
L=43
Q
=344
0
12
3
4
66
7
L=1501234
5
6
7
Q
=120
0
Memory
Bank
Bank
Bank
=
+
+
3x15=45>43
11
CPU
0
3
6
1
4
7
2
5
=
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide12
MethodologySimics
8 4-way superscalar coresL1I (32K)/L1D (32KB)/L2 (1MB) per core
USIMM1channel, 8 ranks, 8 banksBenchmark
SPEC 2006NPBCompared with Temporal Partitioning (HPCA’14)
12Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide13
Increase OS complexity
Results
RANK PARTITIONING
NO PARTITIONING
BANK PARTITIONING
PERFORMANCE
NON-SECUREBASELINE
1.0
0.74
0.48
0.43
0.20
0.40
FS
FS: RD/WR-REORDER
FS: TRIPLE ALTERNATION
TP
TP13100%12%72%
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide14
ConclusionShared MC time-channel attacksFixed Service PolicyMathematical framework to reason about performance and security
Rank-Part: L=7BP: L=15
Re-ordering L=6NP: L=43 Triple Alternation
L=1572% improvement over prior work (TP)
14
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Slide15
Thank You 15
Avoiding Information Leakage in the Memory Controller with Fixed Service Policies