CS 3410 New Instructions Table B Jumps J JR JAL JALR Branches BEQ BNE BLEZ BGTZ BLTZ BGEZ Memory LW LB LBU SW SB However Project 2 is cumulative Logisim RAM LoadUse Hazard ID: 301894
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Slide1
Project 2
CS 3410Slide2
New Instructions (Table B)
Jumps - J, JR, JAL, JALR
Branches - BEQ, BNE, BLEZ, BGTZ, BLTZ, BGEZ
Memory - LW, LB, LBU, SW, SB
However, Project 2
is
cumulative.Slide3
Logisim RAMSlide4
Load-Use HazardSlide5
Load-Use Hazard
Load-use Stall = ID/Ex.MemRead &&
(IF/ID.Ra == ID/Ex.Rd || IF/ID.Rb == ID/Ex.Rd)Slide6
Delay Slot
Branch and Jump instructions have 1 delay slot.Slide7
Control HazardsSlide8
Control Hazards
Simple Solution:
Stall
More Complex Solution (Not required):
Branch Prediction + Zap/FlushSlide9
Data Hazards
Data hazards can occur on branches and jumps!Slide10
Relative vs. Absolute PC
Branches use relative addressing.
Ex: Array indices, A[0], A[1]......A[N].
Jumps use absolute addresses.
Ex: Goto statementsSlide11
Hailstone Programs
Three hailstone MIPS programs required.
An exercise of converting from C to MIPS.
In these you must follow calling conventions.
Do not include a main method!