Registers Shift Register - PowerPoint Presentation

1. Registers

2. Shift RegisterA flip-flop can store 1-bit of digital information. It is also referred to as a 1-bit register.A register contains a group of flip-flops, the number of flip-flops in a register being equal to the number of bits present in the data. Flip-flops are connected in such a way that binary number can be entered into the register and retrieved from the same.A register capable of shifting its binary information either to the right or to the left is called a “Shift register”.

3. Shift registers are classified into the following types depending on the way in which the data is entered and retrieved.1.Serial-in Serial-out(SISO)2.Serial-in Parallel-out(SIPO)3.Parallel-in Serial-out(PISO)4.Parallel-in Parallel-out(PIPO)

4. Serial-in Serial-out (SISO)

5. Serial-in Serial-out (SISO)To set an ‘1’ in a flip-flop ‘A’, hold the J input high and K input low and allow the clock to progress through one cycle. To set ‘0’ in flip-flop ‘A’ hold the J input low and K input high and allow the clock to progress through one cycle. Anytime a ‘1’ exists in flipflop ‘A’ will be shifted to ‘B’ during the next cycle of the clock. Similarly anytime a ‘0’ in flip-flop ‘A’ will be shifted to ‘B’ during next clock cycle. Suppose if it is required to shift the binary number 101 into the register it will be done in the following manner.First of all, the three flip-flops are cleared. Then for flip-flop ‘A’ set the inputs as J=1 and K=0. Thus 1(LSB) will be shifted into ’A’ during first clock pulse. In the mean time B and C will remain in the reset state.(i.e.) ABC=100During the occurrence of the second pulse, make J=0 and K=1. This resets flip-flop ‘A’ . The 1 in ‘A’ will be shifted to ‘B’ and ‘C’ is still in the reset state (i.e.) ABC=010.

6. Serial-in Serial-out (SISO)During the occurrence of third pulse make J=1 & k=0 for flip-flop ‘A’, so that 1 will be entered into ‘A’(MSB) and 0 in A will be shifted to ‘B’ and 1 in ‘B’ will be shifted to ‘C’. i.e. ABC = 101.

7. Serial-in Serial-out (SISO)ABC=110J=0,k=1 =>a=0J=1.k=0 =>a=1, b=0J=1.k=0 =>a=1, b=1, c=0J=0,k=1J=1,k=0J=0,k=1J=0,k=1J=1,k=0J=1,k=0ClkJKABC000000101000210100310110

8. In this way data can be entered serially into the register. To retrieve the data the following procedure is adopted. Now LSB(1) of the data is available at ‘C’. By the application of the next clock pulse the 2nd bit ‘B’ will come to ‘C’. Similarly by applying one more pulse the MSB will be available at ‘C’. Thus by applying two more pulses the data will be retrieved bit by bit.

9. Serial in Parallel out (SIPO)In a SIPO shift register the data will be entered in the same way as in SISO. The output is taken directly from the flip flops in parallel.At the end of the third pulse the data will be available at ABC = 1 0 1 D2 D1 D0

10. Serial in Parallel out (SIPO

11. Parallel in Serial out (PISO)In a PISO shift register loading of data is done with the help of PRESET terminals.When Load=0 data input operation is disabled.When Load =1, the data inputs are entered through the NAND gates into the PRESET terminals of the flip-flops. Load line is enabled for parallel loading. It is always high so that the flip-flop will be either set or reset. Thus without any clock pulse all the bits are loaded simultaneously into the register. For retrieving, the output is obtained at S OUT by the application of clock pulses

12. PISO

13. Parallel-in Parallel-out(PIPO)PIPO Shift Register. In this shift register loading is done as in PISO. For retrieving the data the output of A, B and C are taken as D2, D1and D0 respectively.Using the PIPO Shift Register it is possible to handle the data in any of the four ways discussed above. Hence it is also called an Universal Shift Register.

14. Parallel-in Parallel-out(PIPO)