FrontEnd Electronics for the ATLAS ITk Strip Detector 1June16 Francis Anghinolfi CERN For the ATLAS ITk Strips Community Staves amp Petals Basic Integration Units 1June16 FEE Workshop ID: 784503
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Slide1
ABCStar for ATLAS Strips (Front-End Electronics for the ATLAS ITk Strip Detector)
1-June-16
Francis
Anghinolfi
CERN
For the ATLAS
ITk
Strips Community
Slide2Staves & Petals: Basic Integration Units1-June-16 FEE Workshop
ATLAS Silicon Strips Electronics
2
power
board
EndOfStructure
card
(EoS
)
FE-chip (ABCStar)
hybrid
strip sensors
Hybrid control
chip (
HCC
Star
)
bus
tape
under sensor
module
module
FE-chip
hybrid
EndOfStructure card
(EoS
)
strip
sensors
power
board
Each of 4 barrels will be
segmented
into Staves.
Pictured here is the top side
of a double sided half-Stave.
Two half-Staves butt
together at Z=0, but
don’t connect
electrically.
The End-cap disks will besegmented into petals.Pictured here is the front side of a double- sided Petal.
Z=0 end
1.3m
1.0m
Slide3A Very Large Increase in Size and ComplexityComparing the new ITk tracker to the existing ATLAS SCT:
A factor of 4 more modules to build and a factor of 10 more channels to operate.
Barrel Modules are built on sensors
9.8 cm x 9.8 cm in size.
The inner two barrels have 4 rows of
2.4 cm long strips serviced by 2 readout
hybrids.The outer two barrels have 2 rows of 4.8 cm long strips serviced by one hybrid.End-cap modules use trapezoidal
shaped sensors of varying size to fit
the wedged shape petal.The longest End-cap strip is 5.4 cm long.1-June-16 FEE Workshop
ATLAS Silicon Strips Electronics 3
Readout
ASIC
s (ABC)
Hybrid Control
ASIC
(HCC)
Hybrid
Silicon
Sensor
LV/HV power board
Barrel Module with Short Strips
Slide4ABCStar – New Design
After the first ABC ASICs (named ABC130) were designed and fabricated on the IBM 130nm technology, the ATLAS trigger rate requirement was increased to 1 MHz.
T
he ABC130/HCC readout
architecture could not support this 1 MHz rate and, therefore, a design change was required.
The fundamental change was the interface from ABCs to the HCC as shown here.
Serial transfer of data to the HCC was changed to direct communication from all ABCs to the HCC – hence the new
ABCStar and
HCCStar. The “star” configuration removed a bottleneck in data transfer to the HCC, which had considerable bandwidth still available.
While both ASICs required changes, the HCCStar requires nearly a complete redesign as it must now essentially build events in parallel from fragments coming from all the ABCStar.
1-June-16 FEE WorkshopATLAS Silicon Strips Electronics
4
ABC130
ABCStar
Slide5ABCStar - Standard Binary Readout
The
ABCStar
front-end readout ASIC uses
a similar binary
readout as employed
by the present ATLAS SCT tracker readout. It includes amplifier, discriminator, pipeline for 256
channels, an
event buffer and a cluster algorithm to compress data for output.
It is being designed to support more than one trigger mode:L0 – Capture & readout everything.L0/L1 – Capture data at L0, send
requested data at L1.L0/R3/L1– Capture data at L0, send requested ROI data with priority, send remaining requested data on
L1. The
HCCStar manages these three trigger modes and sends
the appropriate signals to the ABCStar
depending upon what mode is in operation. ABCStar
is built on the GF130nm technology.1-June-16 FEE Workshop
ATLAS Silicon Strips Electronics
5
Slide6ABC130 TestingThe ABCStar and
HCCStar
are still in design.
The ABC130 & HCC130 are being used for testing and to
exercise module assembly and test.
Even if the readout is different, the frontend part of ABCStar and ABC130 should be similar. Characteristics of the frontend are measured with the ABC130.
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ATLAS Silicon Strips Electronics
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Single chip test boardHybrid (endcap)
Module (barrel)
Slide7ABC130 TestingTypical 1 channel data on module : Vt50, Linearity, Noise (threshold scan)
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Slide8ABC130 TestingOne chip data (256 ch.) : Vt50, Linearity, Noise (empty, short strips)
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Slide9ABC130 TestingOne hybrid data (2560 ch.
) : Vt50, Linearity, Noise (empty, short strips)
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Slide10ABC130 TestingThe noise on ABC130 was found to be higher (and gain lower) than expected
Noise performance of the prototype front-end chip and the full
ABC130 front-end was compared.
The prototype front-end allows comparison of performance of
negative & positive signals.
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ATLAS Silicon Strips Electronics
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ABC130 ENC
on prelim. module
Proto ENC for positive signal
Proto ENC for negative signal
ABC130 ENC on hybrid
(ext cap.)
ABC130 receives
negative signal
only, whereas the best performance in design was for
positive signal
Slide11Response curves for positive and negative polarities (same biases – no optimization, 2.5ns calibration edge), measured on the prototype chip
11
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ATLAS Silicon Strips Electronics
Positive input charge:
dynamic range <600mV
Linear range ~450mV (~5fC)
Negative input charge:
dynamic range ~600mV
Linear range ~400mV (~4fC)
Slide12Gain for positive and negative signals (2.5ns CAL edge) – Prototype chip
12
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ATLAS Silicon Strips Electronics
~20% effect!
Slide13ENC for positive and negative signals (2.5ns CAL edge
) – Prototype chip
13
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~20% effect!
Slide14Gain degradation for negative signal (n-on-p detector)
14
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ATLAS Silicon Strips Electronics
Primary candidate: asymmetry caused by active feedback
(compression of the negative polarity signal caused by modulation of
the
transconductance of the active feedback
by the signal)
Slide15Architecture of the single channel
15
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ATLAS Silicon Strips Electronics
Input stage: active feedback
(
as
symmetry
for positive/negative input signals
)
Slide16Transient simulation – analog out
16
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ATLAS Silicon Strips Electronics
Only 6% effect on amplitude, effect not related to the amplitude of the input current
Slight degradation of amplitude for 5ns signal due to ballistic deficit
Input signal
2fC response
NEGATIVE
POSITIVE
Discriminator input
Slide17Performance Difference with Signal PolarityNoise performance is worse after sensor polarity swap: effect of signal compression.
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Effect of compression for negative signals (modulation of feedback transistor gm) simulated at the 6% level, in reality (prototype measurements) as high as 20%.
This can be resolved by changing to a resistive feedback for
ABCStar
.
POSITIVE
NEGATIVE (faster, lower in amplitude, more noisy)
Slide18Irradiation Testing1-June-16 FEE Workshop
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Unexpected noise increase
observed after
ionizing
radiation:
Possible reason:
1/f
noise.
Simulated pre-rad contribution of the
1/f noise to ENC
was at the level of 3%.
Radiation effects on 1/f noise under study.
Some reports for similar
technology (130nm ST) show substantial increase of 1/f noise for regular NMOS devices and no change for the enclosed structures (influence of STI isolation?
)For
new ABC front-end,
all critical (for noise)
NMOS devices will be in enclosed geometry
.
Changes for
the ABCStar front-end
Feedback change to improve gain and noise (+20% impact on power)
ELT layout to reduce excess noise after radiationChannel-to-channel mismatch improvements
Optimisation for the measured detector parameters after full radiations
Slide19Updated Backend for ABCStarThe increase to 1 MHz event
readout
rate was
the main concern for the change to the “star” hybrid architecture.
The L1 rate can be equal to L0 (flush all L0)
The “regional” readout at reduced rate (~10% L0) is maintained. It is perceived as a Priority Readout (L0_Priority)
with low latency (to deliver for the L1track trigger)
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ABC130ABCSTARbaselineABCSTAR
extendedABCSTAR
All L0L0 (event tagging)400KHz
1MHz
1MHz
1MHzR3 (L0-Priority)10KHz100KHz
100KHz-L1 (L0 read)
100KHz400KHz< 1MHz
1MHz
Slide20Event Buffering in ABCStar1-June-16 FEE Workshop
ATLAS Silicon Strips Electronics
20
FE
L0 Pipeline
12.8
μ
s
L0
Event
Buffer
128 slots
Cluster Finder
L1 Queue
R3 Queue
Priority
Start
Read
Serializer
Hit Detect
Address
Low priority
(L1)
read
with tag,
free latency *
P
riority
(R3)
read with tag,
free latency **
Event tagging
Fixed latency
* : up to the maximum possible number of events stored in the event buffer
** : limited by the L1-track construction (5us)
Slide21Managing the 1 MHz L0 RateThe change to the “star” hybrid architecture was not the only concern with the increase to 1 MHz event readout
rate:
T
he
latency requirement for
L0-P trigger is below 5us, to feed data to L1-TrackHere are simulations of the readout time at two different output bandwidths.
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The simulated latency for all data from 99% of all requests to arrive at the end of stave/petal for the highest occupancy Barrel and End-Cap layer module of the ITK as a function of the L0 rate for the scenario where all L0 events are read out
from the detector. Detector occupancies commensurate with a mean occupancy of 200 separate pileup interactions per bunch crossing have been used.
Slide22Data formats and rates1-June-16 FEE Workshop
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One 160Mb/s output signal to the
HCCStar
Physics data contains “cluster packet” of 12 bits (Channel ID + 3 adj. strips)
Full packet made of 4 bits
Header,
16 bits for event ID, then 4 cluster packets max.If more than 4 clusters a second Full packet is generated
The estimated average event size per chip is 2 to 3 clusters (therefore one 56 bits packet)The average data rate at the output of one ABCStar chip is 56 Mb/s
160Mb/s readout rate was rather chosen to reduce the transmission latency for L1-track
68 bits
Slide23L0-TagITk **may**
employ a
scheme to identify L0.
Each L0 trigger will be accompanied by a tag; that tag will be sent back as part of the event data; off-detector electronics will check for matching tags.
The
off-detector electronics then will have responsibility to manage the counter identifiers.
1-June-16 FEE WorkshopATLAS Silicon Strips Electronics
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Group of 4BC
7 bits L0-Tag
L0 distribution in 4BC
Slide24SummaryABCStar is currently under development with the following targets :
Front-end :
A
daptation to the detector signal polarity and to the detector parameters after irradiations
Removal of Excess noise after a few
MradsBack-end :
Low latency Readout for L1_track1MHz full readoutVarious readout scenarios “still” under considerations
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Slide25Backup
BACKUP
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A.A. Grillo
25
Slide26Preamplifier output26
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Preamp response: only 1% effect on amplitude but different timing: negative pulse faster and shorter what can explain difference of 6% after the shaper
NEGATIVE
POSITIVE
Slide27Shaper output
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Shaper response: 6% effect on amplitude and different timing: negative pulse faster and shorter
NEGATIVE
POSITIVE
Slide28Post Irradiation Testing1-June-16 FEE Workshop
ATLAS Silicon Strips Electronics
A.A. Grillo
28
Digital current rise with TID observed in ABC130.
Known effect: see e.g. F. Faccio and G. Cervelli, IEEE Trans. 52.6 (2005) 2413.
Digital current (D) peaks, then recovers. Function of dose rate and temperature. No effect in analogue current (A). ABC tested configured & unconfigured.
Tests underway at expected operating temperature and dose rate at HL-LHC.
At
low temperature/low
dose
rate
(2krads/hour)
Slide29UVM functional verification setup1-June-16 FEE Workshop
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Slide30HCC* Block DiagramThe HCC* provides all I/O control for itself and the multi-ABC* readout system.
Trigger types and commands for configuration, calibration, etc. are received and passed onto ABC*s as needed.
Data from all ABC*s is grouped by event and then sent out.
It is also built on the GF130 nm technology.
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From ABC
Slide31Module is the Basic Building Block
This diagram depicts a short strip barrel module with a blow-up of an ABC130 front-end ASIC.
Each of the two readout hybrids contains 10 ABCs and one HCC module controller ASIC.
Sitting between the two readout hybrids is a
power board.
A long strip barrel module would have one hybrid and one power board.
The power board includes a DC/DC converter to supply 1.5V, an HV switch for sensor bias and an AMAC (Autonomous Monitor & Control) ASIC.
AMAC is powered independent of the DC/DC converter, monitors temperature, voltage, etc. and controls an HV switch and power to hybrid(s).
Bidirectional communication with AMAC is provided via I2C bus from the SCA block of the LpGBT at end of stave or petal. LV to the hybrid and HV to the sensor can be controlled based upon correct temperature and operating voltages and currents.
The End-cap modules differ in the size and shape of the sensor and in the number of ABC ASICs. 1-June-16 FEE Workshop
ATLAS Silicon Strips Electronics 31
Digital Front-end
Power Board: DC/DC, HV Mux, AMAC
Sensor
Short Strip Barrel Module
Power input
7.9mm
6.8mm
SLVS I/O
SLVS I/O
Slide32Stave or Petal ConnectionsOne of Two Sides
Here are all the connections
for readout, control & power.
I will focus on each part one by one.
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ABC*
ABC*
. . .
HCC*
Readout Hybrid
1 or 2 Hybrids
per sensor module
Power Board
DC⁄DC
AMAC
HVsw
Power Supplies
US(A)15
~48V?/~15V?
PP3
DC/DC?
~48V->12V?
PP2
Voltage
Clamp?
DC⁄DC
LpGBT
(1 or 2)
VL+
EOS
HV Supplies
US(A)15
ITk Data Handler
Monitor/Calibration
DCS
ATLAS DAQ
L1 Track
TTC
FELIX
Up to 14 Modules on Bus Tape
Cu-Kapton
Bus Tape
PP1
Service
Module
e
-Links
I2C
Optical
Fibres
High Speed Network
Slide33End of Structure (EOS card) & PP1
Each side of a petal and each side of a half-stave has an EOS card.
Petals with 14 HCC*s (Some modules have 2 hybrids and 2 HCC*s.) and outer barrel half-staves with 14 HCC*s require 1 LpGBT
– Inner barrel half-staves with 28 HCC*s require 2 LpGBTs, each with a complementary number of VL+s.
A DC/DC converter steps down the voltage for the EOS ASICs.
PP1 provides the connection point for harnesses from the outside and the Service Module will provide an
orderly method to tie the PP1 connections to the EOS cards.
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DC⁄DC
LpGBT
(1 or 2)
VL+
EOS
PP1
Service
Module
Optical
Fibres
Concept of PP1 with
Service Module behind