DesignerLevel Verification From Concept to Reality April 30 2014 Ziv Nevo IBM Haifa Research Lab Overview Designerlevel verification DLV DLV tools historical perspective at IBM Our latest recipe ID: 602107
Download Presentation The PPT/PDF document "A New Tool for" is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.
Slide1
A New Tool forDesigner-Level Verification: From Concept to Reality
April 30, 2014
Ziv Nevo
IBM Haifa Research LabSlide2
OverviewDesigner-level verification (DLV)DLV tools: historical perspective at IBM
Our latest recipeSlide3
Designer-level verification (DLV)Slide4
Life without DLV
Logic designer
Verification
engineer
spec
----------
spec
----------
RTLSlide5
Weeks later…
Logic designer
Verification
engineer
spec
----------
spec
----------
fail traceSlide6
DLV ≈ “Developer testing”(standard practice in SW)
Verification
engineer
Logic designer
RTL
Basic checksSlide7
What activities does DLV include?
Observing mainstream behavior
Exploring corner cases
Checking assertions and coverage points
Bug hunting
Debugging
Observation
Lightweight verificationSlide8
Verification: tools of the tradeSimulatorTestbenchHVLMethodologyScriptsFormal
AssertionsCoverage…
Logic designer
Verification
engineerSlide9
DLV: what should the tools be?
Logic designer
Simulator
Testbench
HVL
Methodology
Scripts
Formal
Assertions
Coverage
…Slide10
DLV tools: historical perspective at IBMSlide11
Idea 1: TIMEDIAG (1997)
Specify input value/function/random
Loop cycle (count/random/condition)Slide12
Idea 1: TIMEDIAG (1997)
GenRand
Random instantiation
Simulation
CheckingSlide13
TIMEDIAG ingredients
simulation
Waveform-based interface
complex interleavings
What’s missing?
Interactive define/run/view
Event-guided
test cases
Formal analysisSlide14
What activities does DLV include?
Observing mainstream behavior
Exploring corner cases
Checking assertions and coverage points
Bug hunting
Debugging
Observation
Lightweight verificationSlide15
Idea 2: PathFinder (2002)
Define events
View trace
Find a trace
(formal analysis)Slide16
Idea 2: PathFinder (2002)Main flow:
Specify eventsFind traceView trace
Minor feature:Edit inputs on waveform
SimulateSlide17
PathFinder ingredients
waveform-based interface
simulation
Interactive define/run/view
Event-guided test cases
Formal analysis
What’s missing?
Simple driving
(default is random)
Fast simulation
Integration with common toolsSlide18
What activities does DLV include?
Observing mainstream behavior
Exploring corner cases
Checking assertions and coverage points
Bug hunting
Debugging
Observation
Lightweight verificationSlide19
Another DLV toolSlide20
Jasper VisualizeSlide21
Our latest recipeSlide22
Latest recipe: DiverMain flow
Specify inputs
Simulate
View trace
IBM Debug and Verification Tool for Designers (DIVER)
scenario editor
Specify expected results
View unexpected resultsSlide23
Latest recipe: DiverAdditional variations
Repetitions and delays
Specify events on outputs
Run-to-failure
Simulate or
run formal engine
Assertions and coverageSlide24
Debugging
Import
trace
Trace from simulation of integrated component
Scenario for
designer-level componentSlide25
Diver ingredients
simulation
Waveform-based interface
Interactive define/run/view
Event-guided test cases
Formal analysis
Climate for DLVSlide26
What activities does DLV include?
Observing mainstream behavior
Exploring corner cases
Checking assertions and coverage points
Bug hunting
Debugging
Observation
Lightweight verificationSlide27
ConclusionsDLV activity should scale linearly with the amount of effort spentRecommended recipe:
Waveform-based interfaceInteractive define/run/view
Integration with common tools
Driving inputs
Simulation
Event-based test cases
A touch of formal analysisSlide28
Questions?