BMayerChabotCollegeedu Engineering 43 FETs1 Field Effect Transistors Learning Goals Understand the Basic Physics of MOSFET Operation Describe the Regions of Operation for a MOSFET Device ID: 759691
Download Presentation The PPT/PDF document "Bruce Mayer, PE Registered Electrical &a..." is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.
Slide1
Bruce Mayer, PERegistered Electrical & Mechanical EngineerBMayer@ChabotCollege.edu
Engineering 43
FETs-1
(Field Effect Transistors)
Slide2Learning Goals
Understand the Basic Physics of MOSFET Operation
Describe the Regions of Operation for a MOSFET Device
Use the Graphical LOAD-LINE method to analyze the operation of basic MOSFET Amplifiers
Determine the LARGE-SIGNAL Bias-Point (Q-Point) for MOSFET circuits
Slide3Learning Goals
Use SMALL-SIGNAL models to analyze Several Types of FET AmplifiersCalculate Performance Metrics for various FET Amplifiers Apply FETs to the Design and Construction of CMOS Logic Gates
Slide4Transistor What is it?
Transistor is a contraction for “Transfer Resistor”These devices have THREE connections:InputOutputControlThe transistor’s Fluidic-Analog is a Metering (Needle) Valve (a Faucet)
Slide5The concept of voltage-controlled resistance
An independent Voltage Applied to the Control connection (the “Gate”) regulates the flowof Current Thru the FETdevice
Gate
Drain (or Source)
Source (or Drain)
Slide6Flavors of FETS
Junction Field
Effect Transistor
→ JFET A Normally ON transistorReverse Biasing two PN Junctions will “Pinch Off” a Conducting Channel
Direct (
ohmic
) Connection Between the p & n type silicon
Slide7Flavors of FETS
Depletion ModeMOSFET Another Normally ON transistorApplying a Gate Voltage Drives Carriers OUT of the conducting Channel to turn OFF the transistorNO direct Gate↔Channel ConnectionA Form of an Insulated Gate Field Effect Transistor (IGFET)
Slide8Flavors of FETS
Enhancement Mode MOSFET Normally OFF transistorAnother IGFETApplying a Gate Voltage Attracts & Creates carriers to FORM a conducting Channel to turn ON the transistorThese Make Great Switches
Slide9MOSFET What does that mean?
M → MetalO → OxideS → SiliconF → FieldE → EffectT → TransistorShort for “Transfer Resistor”
N-Channel MOSFET
P-Channel MOSFET
Slide10Enhancement Mode - IGFET
Enhancement Mode IGFETs Normally-Off devices
Applying a Positive Voltage to the Gate will Attract & Create e− to/in the ChannelThis will eventually “invert” a thin region below the gate to N-type, creating a conducting channel between S & DIGFETs are Great SwitchesUsed in almost all digital IC’s
Back-to-Back PN Jcns Between “source” & “drain”
Slide11MOSFET Nomenclature & Dims
We will consider only Enhancement FETs
n+ ≡ Heavily Doped n-Type
An n-Channel (
nFET
)
enhancement mode FET
Slide12MOSFET: Current & Speed
In General the performance of an Enhancement Mode MOSFET:Current Carrying Capacity Increases with Increasing Width, WOn/Off Switching Speed INcreases with DEcreasing Gate Length, LAs of 2014 the minimum (best) value for L was about 16 nm
Slide13MOSFET On/Off Operation
Source
Drain
SiO
2
Insulator (Glass)
Gate
holes
electrons
+5
volts
electrons to be transmitted
Step 1: Apply Gate Voltage
Step 2: Excess electrons surface in channel, holes are repelled.
Step 3: Channel becomes saturated with electrons. Electrons in source are able to flow across channel to Drain.
P
N
N
Slide14nMOSFET Circuit Symbol
n-Channel MOSFETelectrons move from Source→Drain to produce the Drain CurrentPN Junction forms between Substrate and Channel when the FET is “ON”
Schematic Symbol
Drain
Source
Gate
Body
Or
Substrate
Slide15MOSFET Operation: CutOff
As seen in previous diagrams, unpowered MOSFETS have two OPOSING PN junctionsChannel→SourceChannel→Drain With NO Potential applied to the gate No current can flow
From the Previous slide the Minimum Gate Voltage required for current-flow is called the “Threshold” Voltage,
V
to
or
V
th
A MOSFET
with
V
GS
<
V
th
is “
CutOff
”
i.e.; The MOSFET is Off, and the Drain Current,
i
D
= 0
Slide16MOSFET Circuit in CutOff
The Diagram at Right shows an nMOSFET in CutOffFor vGS<Vto the PN Jcn between the Drain & Channel is Reversed Biased by vDS and NO Current flowsVto (or Vth) is typically 0.5-5 Volts
Mathematically this is simple; in CutOff, the Drain Current
Slide17Power MOSFET Data Sheet
Slide18CutOff Summarized
VGS < Vto → No Drain Current Flows
Slide19MOSFET IN Triode (Ohmic) Region
In this case the nMOSFET Voltage conditions:Electrons are ATTRACTED to the Positive-Gate and a thin Conducting Channel FormsIn this Region the Drain Current depends on BOTH vDS and vGS Fluid Analogy → needle valve
Slide20nMOSFET in TriOde Operation
When vGS > Vto a thin & ≈uniform conducting channel forms below the gate
Slide21Triode Operation
When
v
GS
>
V
to
a conducting channel forms below the gate.
That is, the “type” of the silicon is INVERTED from
p
-Type to
n
-Type
Thus this conducting Channel is often called an “Inversion Layer”
The greater
v
GS
The more the conducting channel thickens
The Channel
resistance
is thus a function of
v
GS
as thicker channels have lower R
Slide22TriOde Operation
In the Triode Region, iD increases forIncreasing vGSIncreasing vDSThus current thru the device depends on the voltage at ALL three connections as long as vDS < (vGS − Vto)
The Three-Connection dependency is why this region is called TRIODE
Slide23TriOde Operation
In TriOde Operation, the iD curve is a concave-down Parabola given byWhereThe Device TransConductance Parameter, KP, Depends on the
Construction of the FETKP for nFETs is typically 10-100 µA/V2
Slide24PinchOff
In order to form a complete channel, every point, x, along the channel must have a voltage difference greater than VtoThat is, needThe greater this qty, the thicker the conducting Layer
Now as vDS is increased eventually at x = L where vchan = vDSThe Channel Thickness goes to ZERO. This is called PINCH-OFF
Slide25PinchOff Illustrated
The layer is THICKEST at the Source and ZERO at the Drain whenThus Have PinchOff when, as vDS rises
At this Point the channel is Very Thick at the Source-End, and Zero-Thick at the Drain End →
Pinched
Off
at Drain
Slide26TriOde Region Summarized
vDS ≤ (vGS − Vto) → iD = f(vDS , VGS)
Start
of ←
TriOde
Channel Formation
Finish
of
TriOde
→ Drain
PinchOff
Slide27PinchOff iD Saturation
As vDS increases the “PinchOff Point”, xpop, Moves BACKWARDS towards the SourceOnce the channel Pinches Off, the drain current, iD, NO Longer increases with increasing vDS
In other words, for a given vGS, the Current “Saturates” (stays constant) After PinchOff as shown below
does NOT depend
on
nMOSFET complete vi Curve
Slide29MOSFET Operation Summary
Cut-Off Region – In this region the gate voltage is less than the Threshold voltage Vto and therefore very little current flows.Triode Region – In this mode the device is operating below pinch-off and is effectively a variable resistor.Saturation Region – This is the main operating region for the device. The drain voltage has to be greater than the gate voltage minus the Threshold voltage.
In Saturation the Drain Current,
, is FREE of . ONLY can alterthe drain current
Operation in Saturation
Notice that in SAT iD varies with vGS Note that vDS does NOT appear in this EquationvDS (on vi curve) does NOT affect iD after Channel-PinchOff
In SAT a MOSFET is a true 3-terminal device; current depends ONLY on the CONTROL Signal, vGS
Slide31Saturation Summarized
vDS ≥ (vGS − Vto) → iD ≠ f(vDS)
PinchOff
Moved BACK from Drain
Slide32Triode↔Saturation Boundary
At the Boundary Line the nMOSFET just Barely Pinches Off at the Drain end thus:By KVLSubstituting FindOr at the Boundary
Boundary Line
Sub for
v
GS
into
i
D,sat
Eqn
+
nFET KVL
TriOde↔Saturation Boundary
Then then along the BoundaryThe Boundary is thus described by a Concave-UP Parabola that passes thru the origin
Boundary Line
Slide35Example 12.1 make vi Plot
Use Parameters from Example 12.1 to plot in MATLAB the vi Curve for a nMOSETThe ParaMetersW = 160 µmL = 2 µm (pretty large)KP = 50 µA/V2Vto = 2VPlot has multiple operating regions → must concatenate
L
W
W/L Aspect Ratio = 80
Slide36The completed Plot
Slide37MATLABCode-1
% Bruce Mayer, PE
% ENGR43 * 14Jan12
% file = nMOSFET_Plot_ex12_1_1201.m
W = 160;
% µm
L = 2;
% µm
KP = 50;
% µA/sq-V
Vto
=
2;
% V
%
% calc Parameter K
K = (W/L)*KP/2;
% µA/
sqV
)
%
% set
vGS
values that exceed
CutOff
at 2V
vGS = [3, 4, 5, 6];
%
% calc boundary Triode/Sat boundary by finding
iD
at the START of sat
% region
iDsat_uA
= K*(
vGS-Vto
).^2;
% in µA
iDsat_mA
=
iDsat_uA
/1000
%
% show cutoff line
vDSco
=
linspace
(0,10, 200);
iDco
= zeros(200);
%
DeBug
Command => plot(
vDSco
,
iDco
, '
LineWidth
', 3)
%
% Calc
iD
in
TriOde
Region for
vGS
>
Vto
(Pinched off at Drain)
%* use
eqn
(12.6) in text
vDSsat
=
sqrt
(
iDsat_uA
/K)
% must take care with units
%
plot(
vDSsat,iDsat_mA
,
'--*'
,
'
LineWidth
'
, 3), grid,
xlabel
(
'
vDSsat
'
),
ylabel
(
'
iDsat
'
)
disp
(
'showing Triode-Sat Boundary - Hit any key to continue'
)
pause
%
Slide38MATLABCode-2
% then
iD
in triode region
vDSt1 =
linspace
(0,
vDSsat
(1));
% V
vDSt2 =
linspace
(0,
vDSsat
(2))
vDSt3 =
linspace
(0,
vDSsat
(3))
vDSt4 =
linspace
(0,
vDSsat
(4))
iDt1_mA = K*(2*(
vGS
(1)-
Vto
)*vDSt1-vDSt1.^2)/1000;
%
mA
iDt2_mA = K*(2*(
vGS
(2)-
Vto
)*vDSt2-vDSt2.^2)/1000;
%
mA
iDt3_mA = K*(2*(
vGS
(3)-
Vto
)*vDSt3-vDSt3.^2)/1000;
%
mA
iDt4_mA = K*(2*(
vGS
(4)-
Vto
)*vDSt4-vDSt4.^2)/1000;
%
mA
%
%
%
DeBug
Command =>plot(vDSt1,iDt1_mA, vDSt4,iDt4_mA)
%
% use
TwoPoint
Plots in Sat
iDsat1 =[
iDsat_mA
(1),
iDsat_mA
(1)]
iDsat2 =[
iDsat_mA
(2),
iDsat_mA
(2)]
iDsat3 =[
iDsat_mA
(3),
iDsat_mA
(3)]
iDsat4 =[
iDsat_mA
(4),
iDsat_mA
(4)]
vDSsat1 = [
vDSsat
(1), 10]
vDSsat2 = [
vDSsat
(2), 10]
vDSsat3 = [
vDSsat
(3), 10]
vDSsat4 = [
vDSsat
(4), 10]
%
Slide39MATLABCode-3
%
% Now Concatenate to
cover
Triode & Saturation Regions
iD1 = [iDt1_mA,iDsat1]
vDS1 = [vDSt1, vDSsat1]
iD2 = [iDt2_mA,iDsat2]
vDS2 = [vDSt2, vDSsat2]
iD3 = [iDt3_mA,iDsat3]
vDS3 = [vDSt3, vDSsat3]
iD4 = [iDt4_mA,iDsat4]
vDS4 = [vDSt4, vDSsat4]
%
%
% Finally Make Plot
plot(
vDSco
,
iDco,
'b
'
, vDS1, iD1,
'c'
, vDS2, iD2,
'g'
, vDS3, iD3,
'm'
, vDS4, iD4,
'r'
,
'
LineWidth
'
, 3),
...
grid,
xlabel
(
'
vDS
(Volts)'
),
ylabel
(
'
iD
(
mA
)'
), title(
'
nMOSFET
vi Curve - Ex 12.1'
),
...
gtext
(
'VGS<
Vto
'
),
gtext
(
'
vGS
=3V'
),
gtext
(
'
vGS
=4V'
),
gtext
(
'
vGS
=5V'
),
gtext
(
'
vGS
=6V'
)
Slide40pMOSFET
A “pMOS” FET is the “Complement” to the nMOS version. The channel is normally n-Type and a hole-populated conducting Channel is formed by applying a NEGATIVE vGSBasically the pMOS version looks like the nMOS FET with voltage-polarities inverted
Channel
pMOSFET
Circuit
Symbol
Slide41p & n MOSFET Comparison
Concave DOWN Parabola
Concave UP Parabola
BOUNDARY →
All Done for Today
3 & 4
ConnectionnFET
Slide43Bruce Mayer, PERegistered Electrical & Mechanical EngineerBMayer@ChabotCollege.edu
Engineering 43
Appendix
Diode vi Curves
Slide44Slide45Slide46