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and Their Models Chapter Outline Nanometer transistor behavior and models Subthreshold currents and leakage Variability Device and technology innovations Nanometer Transistors and Their Models ID: 329468

gate leakage threshold current leakage gate current threshold drain channel technology power ref transistor high 100 control impact design devices ieee mos

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Slide1

Nanometer Transistors

and Their ModelsSlide2

Chapter Outline

Nanometer transistor behavior and models

Sub-threshold currents and leakage

Variability

Device and technology innovations Slide3

Nanometer Transistors and Their Models

Emerging devices in the sub-100 nm regime post

challenges

to low-power design

Leakage

Variability

Reliability

Yet also offer some opportunities

Increased mobility

Improved control (?)

State-of-the-art low-power design should build on and exploit these properties

Requires clear understanding and good modelsSlide4

The Sub-100 nm transistor

Velocity-saturated

Linear dependence between

I

D

and

V

GS

Threshold voltage

V

TH

strongly impacted by channel length

L

and

V

DS

Reduced threshold control through body biasing

Leaky

Subthreshold

leakage

Gate leakage

Decreasing

I

on

over

I

off

ratioSlide5

I

D

versus

V

DS

for 65 nm bulk NMOS transistor

I

D

linear function of

V

GS

VGS = 0.8

VGS = 0.6

VGS = 0.4

VGS = 1.0

Early saturation

Decreased

output resistanceSlide6

Drain Current under Velocity Saturation

Good model, could be used in hand or

Matlab

analysis

with

[Ref:

Taur-Ning

, ’98]Slide7

Models for sub-100 nm CMOS transistors

Further simplification:

The unified model

– useful for hand analysis

Assumes

V

DSAT

constant

[Ref: Rabaey, DigIC’03]Slide8

Models for

sub-100

nm CMOS transistors

0

100

200

300

400

500

600

700

0

0.2

0.4

0.6

0.8

1

1.2

V

DS

[V]

0.4V

0.6V

0.8V

1.0V

1.2V

simulation

unified model

linear

saturation

vel. saturation

V

DSAT

I

DS

[

m

A]Slide9

Alpha Power Law Model

Alternate approach, useful for hand analysis of propagation delay

Parameter

a

is between

1 and 2.

In 65nm – 180 nm CMOS technology

a

~

1.2..1.3

[Ref: Sakurai

, JSSC’90]

This is not a physical model

Simply empirical:

Can fit (in minimum mean squares sense) to variety of ’s, VTHNeed to find one with minimum square error – fitted

VTH can be different from physicalSlide10

Output Resistance

Drain current keeps increasing beyond the saturation point

Slope in I-V characteristics caused by:

Channel length modulation (CLM)

Drain-induced barrier lowering (DIBL)

.

[Ref: BSIM

3v3 Manual]

The simulations show approximately linear dependence of

I

DS

on VDS

in saturation (modeled by l factor)Slide11

Thresholds and Sub-Threshold Current

Drain current vs. gate-source voltage

V

THZ

V

DS

= 1.2VSlide12

Forward and Reverse Body Bias

Threshold value can be adjusted through the 4

th

terminal,

the transistor body.

Forward bias

Reverse bias

Forward bias restricted by SB and DB junctionsSlide13

Evolution of Threshold Control

-0.5

0

0.5

-0.1

-0.05

0

0.05

0.1

0.15

V

BB

(V)

D

V

TH

(V)

130 nm

90 nm

65 nm

Body biasing effect diminishes with technology scaling below 100 nm.

No designer control at all in FD_SOI technology

210 mV

95 mV

55 mVSlide14

Impact of Channel Length on Threshold Voltages

L

Long-channel threshold

L

min

With halo implants

(for small values of V

DS

)

Partial depletion of channel due to source and drain junctions larger in short-channel devices

Simulated

V

TH

of 90 nm technologySlide15

Impact of Channel Length on Threshold Voltages

50% increase in channel length

decreases leakage current by almost factor 20 (90 nm)Slide16

Drain-Induced Barrier Lowering (DIBL)

In a short channel device, source-drain distance is comparable to the depletion region widths, and the drain voltage can modulate the threshold

V

TH

=

V

TH0

-

l

dVDS

Channel

L (D)

0 (S)

Long channel

Short channel

V

ds

= 0.2V

V

ds

= 1.2VSlide17

MOS Transistor Leakage Components

G

D

S

B(W)

Gate leakage

D-S leakage

Junction

leakageSlide18

Sub-threshold Leakage

Subthreshold slope

S

=

kT/q

ln10 (1+

C

d

/

C

i

)

Drain leakage current is exponential with

VGSSubthreshold swing S is ~70..100mV/dec

VDS = 1.2V

G

S

D

Sub

C

i

C

d

The transistor in “weak inversion”Slide19

Impact of Reduced Threshold Voltages on Leakage

4 orders of magnitude

300 mV

Leakage: sub-threshold current for

V

GS

= 0Slide20

Subthreshold Current

Subthreshold behavior can be modeled physically

with

n

the

slope factor

(≥ 1, typically around 1.5), and

Very often expressed in base 10

the

subthreshold swing

, ranging between 60mV and 100mV

with

1 for

V

DS

> 100 mVSlide21

Subthreshold Current - Revisited

Drain-Induced Barrier Lowering (DIBL)

Threshold reduces approximately linearly with

V

DS

Body Effect

Threshold reduces approximately linearly with

V

BS

Leading to:

Leakage exponential function of drain and bulk voltagesSlide22

Subthreshold Current as Function of

V

DS

I

D

versus

V

DS

for minimum size 65 nm NMOS transistor

(

VGS = 0)

ld = 0.18S = 100 mV/dec

DIBL

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

x 10

-9

V

DS

(V)

I

D

(A)

Two effects:

diffusion current (like bipolar transistor)

exponential increase with

V

DS

(DIBL)

3-10x in

current

technologiesSlide23

Gate-Induced Drain Leakage (GIDL)

Excess drain current is

observed,

when gate voltage is

moved below

V

TH

,

and moves to negative values (for NMOS)

More outspoken for larger values of VDS (or GIDL ~ V

DG)High electrical field between G and D causes tunneling and generation of electron-hole pairs

Causes current to flow between drain and bulkInvolves many effects such as band-to-band direct tunneling and trap-assisted tunneling

[Ref: J. Chen, TED’01]

© IEEE 2001Slide24

Combining all Drain Leakage Effects

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

10

-12

10

-10

10

-8

10

-6

10

-4

V

GS

(V)

I

D

(A)

V

DS

= 0.1 V

V

DS

= 1.0 V

V

DS

= 2.5 V

90 nm NMOS

GIDLSlide25

Gate Leakage

Silicon substrate

1.2 nm SiO

2

Gate

Scaling leads to

gate-oxide

thickness of couple of molecules

MOS digital design has always been based on assumption of infinite input resistance!

Hence: Fundamental impact on design strategy!

Causes gates to leak!

[Ref: K.

Mistry

, IEDM’07]

Introduction of high-

k

dielectricsSlide26

Gate Leakage Mechanisms

Direct Oxide tunneling dominates for lower

T

ox

[Ref:

Chandrakasan-Bowhill

, Ch3,

‘00

]

© IEEE

2000Slide27

Direct Oxide Tunneling Currents

V

DD

J

G

(A/cm

2

)

0

0.3

0.6

0.9

1.2

1.5

1.8

10

-9

10

-6

10

-3

10

0

10

3

10

6

10

9

t

ox

0.6 nm

0.8 nm

1.0 nm

1.2 nm

1.5 nm

1.9 nm

V

DD

trend

[Courtesy: S. Song, 01]

Also: - Gate tunneling strong function of temperature

- Larger impact for NMOS than PMOS

J

G

: exponential function of oxide thickness and applied voltageSlide28

High-k Gate Dielectric

Equivalent Oxide Thickness = EOT =

t

ox

=

t

g

* (3.9/

e

g), where 3.9 is relative permittivity of SiO

2 and eg is relative permittivity of high-k materialCurrently SiO2/Ni; Candidate materials: HfO

2 (eeff~15 - 30); HfSiOx

(eeff~12 - 16)Often combined with metal gate

Electrode

Si substrate

t

ox

SiO

2

t

g

High-k Material

Electrode

Si substrate

Reduced Gate Leakage for Similar Drive CurrentSlide29

High-k Dielectrics

Silicon substrate

1.2 nm SiO

2

Gate

Silicon substrate

Gate electrode

3.0nm High-k

Buys at a few generations of technology scaling

[Courtesy: Intel]

High-k vs. SiO

2

Benefits

Gate capacitance

60% greater

Faster transistors

Gate dielectric leakage

> 100% reduction

Lower powerSlide30

Gate Leakage Current Density Limit versus Simulated Gate Leakage

[Ref:

ITRS 2005]Slide31

Temperature Sensitivity

Increasing temperature

Reduces mobility

Reduces

V

TH

I

ON

decreases with temperatureIOFF

increases with temperature

0

10

20

30

40

50

60

70

80

90

100

0

1

2

3

4

5

6

7

8

9

10

x 10

4

Temp(°C)

Ion/Ioff

90 nm NMOSSlide32

Variability

Scaled device dimensions leading to increased impact of variations

Device physics

Manufacturing

Temporal and environmental

Impacts performance, power (mostly leakage) and manufacturing yield

More outspoken in low-power design due to reduced supply/threshold voltage ratiosSlide33

Variability Impacts Leakage

130nm

30%

5X

0.9

1.0

1.1

1.2

1.3

1.4

1

2

3

4

5

Normalized Leakage (Isb)

Normalized Frequency

Threshold variations have exponential impact on leakage

[Ref:

P.

Gelsinger

,

DAC’04

]Slide34

Variability Sources

Physical

Changes in characteristics of devices and wires.

Caused by IC manufacturing process, device physics & wear-out (electro-migration).

Time scale: 10

9

sec (years).

Environmental

Changes in operational conditions (modes), V

DD

, temperature, local coupling.Caused by the specifics of the design implementation.Time scale: 10−6 to 10−9 sec (clock tick).Slide35

Variability Sources and their Time Scales

Signal Coupling

Supply

/

PackageNoise

Temperature ─

Modal Operation

Manufacturing ─

Wear-out

10

-10

-10

-8

10

-7

-10

-5

10

-4

-10

-2

10

5

-10

7Slide36

Process Variations

Percentage of total variation accounted for by within-die variation(device and interconnect)

[Courtesy: S.

Nassif

, IBM]

Technology Node (nm)

0%

10%

20%

30%

40%

250

180

130

90

65

L

eff

w

,

h

,

T

ox

,

V

th

3

/meanSlide37

Threshold Variations Most Important for Power

[Courtesy: S.

Borkar

, Intel]

Decrease of random dopants in channel increases impact of variation on threshold voltageSlide38

Device and Technology Innovations

Power challenges introduced by nanometer MOS transistors can be partially addressed by new device structures and better materials

Higher mobility

Reduced leakage

Better control

However …

Most of these techniques provide only a one (two) technology generation boost

Need to accompanied by circuit and system level methodologiesSlide39

Device and Technology Innovations

Strained silicon

Silicon-on-insulator

Dual-gated devices

Very high mobility devices

MEMS - transistors

DG-SOI

FinFET

GP-SOISlide40

Strained Silicon

Improved ON-Current (10-25%) translates into:

84-97% leakage current reduction

or 15% active power reduction

[Ref:

P.

Gelsinger

, DAC’04

]Slide41

Strained Silicon

Transistor Drive Current

(

mA

/

m

m)

Transistor Leakage Current

(

nA

/mm)

[Ref: S. Chou, ISSCC’05]

Improves Transistor Performance and/or Reduces Leakage

1000

100

10

1

0.2

0.4

0.8

0.6

1.0

1.2

1.4

1.6

Std

Strain

Std

Strain

PMOS

N

MOS

+25% I

ON

+10% I

ON

0.04 × I

OFF

0.20 × I

OFFSlide42

Beyond Straining

Hetero-junction devices allow for even larger carrier mobility

[Courtesy:

G. Fitzgerald

(MIT), K.

Saraswat

(Stanford)]

Example: Si-Ge-Si hetero-structure channelSlide43

Silicon-on-Insulator (SOI)

Reduced capacitance (source and drain to bulk) results in lower dynamic power

Faster sub-threshold roll-off (close to 60 mV/decade)

Random threshold fluctuations eliminated in fully depleted SOI

Reduced impact of soft-errors

But

More expensive

Secondary effects

Thin Oxide

Substrate

FD

S

D

G

Thin

silicon

layer

[Courtesy: IBM]Slide44

Example: Double-Gated Fully-Depleted SOI

well

contact

well

G (Ni silicide)

thin BOX

(

<

10nm)

thin SOI (

<

20 nm)

well

STI

sub

STI

STI

sub

D

S

V

T

control

dopant

(10

18

/cm

3

)

[

Ref:

M.

Yamaoka

, VLSI’04, R. Tsuchiya, IEDM’04]

90 nm bulk

65 nm bulk

45 nm bulk

32 nm bulk

65 nm FD-SOI

45 nm FD-SOI

32 nm FD-SOI

Standard deviation (a.u.)

2

1

0

(

V

T

)

int

ext

int

ext

(

V

T

)

0.5

0.4

0.3

0.5

High dose

Low dose

V

DD

= 1.0 V

w/o

t

SOI

= 20 nm

t

BOX

= 10 nm

0.2

0.1

0.0

-0.1

1.0

0.0

-0.5

-1.0

0.6

Well-bias voltage

V

well

(V)

Threshold voltage

V

T

(V)

Buried gate provides accurate threshold control over wide range

© IEEE 2004Slide45

FinFETs – An Entirely New Device Architecture

UC Berkeley, 1999

Suppressed short-channel effects

Higher on-current for reduced leakage

Undoped channel – No random dopant fluctuations

S

= 69

m

V

/

dec

[Ref:

X. Huang

,

IEDM’99]

© IEEE 1999Slide46

BackGated FinFET

Drain

Source

Gate

Fin Height H

FIN

= W/2

Gate length = Lg

Fin Width = T

Si

Drain

Gate1

Source

Switching

Gate

Gate2

Vth Control

Fin Height H

FIN

= W

Gate length = Lg

Back-gated (BG) MOSFET

Double-gated (DG) MOSFET

Independent front and back gates

One switching gate and

Vth

control gate

Increased threshold controlSlide47

New Transistors: FINFETs

Intel tri-gate

Berkeley PMOS FINFET

Manufacturability still an issue – may even cause more variations

Gate

Drain

Source

[Courtesy: T.J. King, UCB; Intel]Slide48

Some Futuristic Devices

FETs with subthreshold swing < kT/q (I-MOS)

V

S

= -1V

V

D

= 0V

5 mV/dec.

L

I

= 25 nm

L

GATE

= 25nmtox = 1 nmt

si = 25 nm

ON

OFF

I-MOS

MOS

N

+

P

+

I-MOS

Buried-Oxide

Poly

Impact Ionization Region

[Courtesy: J. Plummer, Stanford]

Zero OFF-current transistor

Uses MEMS technology to physically change

gate

control.

Allows for zero-leakage sleep

transistors and advanced memories

[Ref: Abele05, Kam05]

© IEEE 2005Slide49

Summary

Plenty of opportunity for scaling in the nanometer age

Deep-submicron behavior of MOS transistors has substantial impact on design

Power dissipation mostly impacted by increased leakage (SD and gate) and increasing impact of process variations

Novel devices and materials will ensure scaling to a few nanometersSlide50

References

Books and Book Chapters

A.

Chandrakasan

, W.

Bowhill

, F. Fox (eds.), “Design of High-Performance Microprocessor Circuits”, IEEE Press 2001.

J. Rabaey, A.

Chandrakasan

, B. Nikolic, “Digital Integrated Circuits: A Design Perspective,” 2

nd ed, Prentice Hall 2003.Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices,Cambridge

University Press, 1998.ArticlesAbele, N.; Fritschi, R.; Boucart

, K.; Casset, F.; Ancey, P.; Ionescu, A.M., “Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor,” Proc. Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp 479-481, Dec. 2005

BSIM3V3 User Manual, http://www.eecs.berkeley.edu/Pubs/TechRpts/1998/3486.htmlJ.H. Chen et al, “An Analytic Three-Terminal Band-to-Band Tunneling Model on GIDL in MOSFET,” IEEE Trans. On Electron Devices, Vol. 48 No 7, pp. 1400-1405, July 2001.

S. Chou, “Innovation and Integration in the Nanoelectronics Era,” Digest ISSCC 2005, pp. 36-38, February 2005.P.

Gelsinger, “Giga-scale Integration for Tera-Ops Performance,” 41st DAC Keynote, DAC, 2004, (www.dac.com)

X. Huang et al (1999) "Sub 50-nm FinFET: PMOS“, International Electron Devices Meeting Technical Digest, p. 67. December 5-8, 1999.

International Technology Roadmap for Semiconductors, http://www.itrs.net/H. Kam et al., “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics, “ IEDM Tech. Digest, pp. 463- 466, Dec. 2005

.K. Mistry et al, “A 45nm Logic Technology with High-

k+Metal

Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100%

Pb

-free

PackagingProceedings

,” IEDM, pp. 247, Washington, Dec. 2007.

Predictive Technology Model (PTM), http://

www.eas.asu.edu/~ptm

/

T

. Sakurai and R. Newton. “Alpha-power law

mosfet

model and its applications to

cmos

inverter delay and other formulas.,”

IEEE Journal of Solid-State Circuits

, 25(2), 1990.

R. Tsuchiya et al,

“Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high- performance application featuring wide-range back-bias control,” Proceedings IEDM 2004, pp. 631-634, Dec. 2004

.

M. Yamaoka et al, “Low

power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology,” Digest of Technical Papers VLSI Symposium, pp. 288-291, June 2004.

W

. Zhao, Y. Cao, “New generation of predictive technology model for sub-45nm early design exploration,”

IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006