Low Capacitance Low Charge Injection V V CMOS Dual SPDT Switch ADG Rev - PDF document

Data Sheet ��Rev. | Page of Y Version Parameters25°C40°C to +85°C40°C to +125°CUnitTest Conditions/Comments POWER REQUIREMENTS= +16.5 V, V16.5 V 0.001 µA typ Digital inputs = 0 V or V 1.0 µA max µA typ Digital inputs = 5 V µA max 0.001 µA typ Digital inputs = 0 V or V 1.0 µA max 0.001 µA typ Digital inputs = 5 V 1.0 µA max �� &#x/MCI; 85;&#x 000;&#x/MCI; 85;&#x 000; &#x/MCI; 87;&#x 000;&#x/MCI; 87;&#x 000;1 Temperature range for Y version is to +Guaranteed by design;not subject to production test. Data Sheet ��Rev. | Page of SINGLE SUPPLY= 1210%, VV, GND = 0V, unless otherwise notedTable Y Version Parameters25°C40°C to +85°C40°C to +125°CUnitTest Conditions/Comments ANALOG SWITCH Analog Signal Range0 V to V On Resistance (Rtyp= 0 V to 10 V, IFigure max= 10.8 V, V= 0 V On Resistance Match Between Channels (4.5typ= 0 V to 10 V, I max On Resistance Flatness (RFLAT(ON)typ= 3 V, 6 V, 9 V, I1 mA LEAKAGE CURRENTS = 13.2 V Source Off Leakage, I(Off)±0.02 nA typ= 1 V/10 V, V= 10 V/1 V; Figure ±0.1±0.6nA max Drain Off Leakage, I(Off)±0.02 nA typ= 1 V/10 V, V= 10 V/1 V; Figure ±0.1±0.6nA max Channel On Leakage, I(On)±0.02 nA typ= 1 V or 10 V, Figure ±0.2±0.6nA max DIGITAL INPUTS Input High Voltage, VINH2.0 V min Input Low Voltage, VINL0.8 V max Input Current, IINLor IINH0.001 µA typINLor VINH ±0.1 µA max Digital Input Capacitance, C pF typ DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSOFFns typ = 300 , C= 35 pF ns max = 8 V; Figure Transition Time, tTRANSOFFns typ = 300 , C= 35 pF ns max = 8 V; Figure BreakBeforeMake Time Delay, t ns typ= 300 = 35 pF ns min= 8 V; Figure Charge Injection0.8 pC typ= 6 V, R= 0 = 1 nF; Figure Off Isolation 75 dB typ R L = 50  , C L = 5 pF, f = 1 MHz; Figure 26 ; ChannelChannel Crosstalk dB typ= 50 = 5 pF, f = 1 MHz; Figure 3 dB Bandwidth MHz typ= 50 = 5 pF; Figure (Off) 1.6pF typ f = 1 MHz; V= 6 V 1.9pF maxf = 1 MHz; V= 6 V (On)pF typ f = 1 MHz; V= 6 V 4.9pF maxf = 1 MHz; V= 6 V POWER REQUIREMENTS = 13.2 V 0.001 µA typDigital inputs = 0 V or V 1.0 µA max µA typDigital inputs = 5 V µA max �� &#x/MCI; 29; 00;&#x/MCI; 29; 00;1 Temperature range for Y version is to +Guaranteed by design;not subject to production test Data Sheet ��Rev. | Page of ABSOLUTE MAXIMUM RATINGS= 25°Cunless otherwise notedTable ParameterRating to V to GND0.3 V to +25 V to GND+0.3 V to Analog Inputs0.3 V to V+ 0.3 V or 30 mA, whichever occurs first Digital InputsGND 0.3 V to V+ 0.3 V or 30 mA, whichever occurs first Peak Current, S or D100 mA (pulsed at 1 ms, 10% duty cycle max) Continuous Current per Channel, S or D25 mA Operating Temperature Range Automotive (Y Version)  40°C to +125°C Storage Temperature Range65°C to +150°C Junction Temperature150°C Lead TSSOP, Thermal Impedance112°C/W Lead LFCSP, Thermal Impedance80°C/W Reflow Soldering Peak Temperature, Pb Free260°C �� &#x/MCI; 37;&#x 000;&#x/MCI; 37;&#x 000;1 Overvoltages at IN, Sor D areclamped by internal diodes. Current mustbe limited to the maximum ratings given.Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.ESD CAUTION TRUTH TABLE FOR SWITCHTable Switch ASwitch B Off Off Data Sheet ��Rev. | Page of TERMINOLOGYThe positive supply current. The negative supply current. The analog voltage on Terminals D and The ohmic resistance between D and S. FLAT(ON)Flatness is defined as the difference between the maximum and minimum value of onresistance as measured over the specified analog signal range. (Off)The source leakage current with the switch(Off)The drain leakage current with the switchoff.(On)The channel leakage current with the switchon.INLThe maximum input voltage for Logic 0.INHThe minimum input voltage for Logic 1.INLINHThe input current of the digital input. (Off)The off switch source capacitance, measured with reference to ground. (Off)The off switch drain capacitance, measured with reference to ground. (On)The on switchcapacitance, measured with reference to ground. The digital input capacitance. TRANSThe delay time between the 50% and 90% points of the digital input and switch condition when switching from one address state to another.Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal thatis coupled through from onechannel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3dB. On Response The requency response of the on switch. Insertion LossThe loss due to the on resistance of the switch. THD + NThe ratio of the harmonic amplitude plus noise of the signal to the fundamental. Data Sheet ��Rev. | Page of TYPICAL PERFORMANCE CHARACTERISTICS SOURCE OR DRAIN VOLTAGE (V)ON RESISTANCE ()2001000–18–15–12–9–6–3121590631804776-011 18016014012080604020 TA = 25C VDD = 15VVSS =–15V VDD = 16.5VVSS =–16.5V VDD = 13.5VVSS =–13.5V Figure . On Resistance as a Function of V) for DualSupply SOURCE OR DRAIN VOLTAGE (V)ON RESISTANCE ()6003000–6–4–2402604776-012 500400200100 TA = 25C VDD = 5VVSS =–5V VDD = 5.5VVSS =–5.5V VDD = 4.5VVSS =–4.5V Figure . On Resistance as a Function of V) for Dual Supply SOURCE OR DRAIN VOLTAGE (V)ON RESISTANCE ()45025030000246128101404776-013 40035015020010050 TA = 25C VDD = 12VVSS = 0V VDD = 13.2VVSS = 0V VDD = 10.8VVSS = 0V Figure On Resistance as a Function of V) for SingleSupply TEMPERATURE (C)ON RESISTANCE ()2500–15–10–510051504776-014 15020010050 TA = +25C TA = +85C TA = +125C TA =–40C VDD = 15VVSS =–15V Figure On Resistance as a Function of V) for Different Temperatures, Dual Supply TEMPERATURE (CON RESISTANCE ()600002410681204776-015 300400200500100 TA = +25C TA = +85C TA = +125C TA =–C VDD = 12VVSS = 0V Figure . On Resistance as a Function of V) for Different Temperatures, Single Supply TEMPERATURE (C)LEAKAGE (nA)0.20–0.2002040100608012004776-016 00.050.100.15–0.05–0.15–0.10 ID, IS(ON) IS(OFF) VDD = 15VVSS =–15VVBIAS = +10V/–10V Figure Leakage Currents as a Function of Temperature, Dual Supply Data Sheet ��Rev. | Page of TEMPERATURE (C)LEAKAGE (nA)0.35–0.1002040100608012004776-017 0.200.150.100.0500.250.30–0.05 ID, IS(ON) IS(OFF) VDD = 12VVSS = 0VVBIAS = 1V/10V Figure 10. Leakage Currents as a Function of Temperature, Single Supply LOGIC, INX (V)IDD (A)60504030102000246810121404776-018 VDD = 12VVSS = 0V VDD = 15VVSS =–15V IDD PER CHANNELTA = 25C Figure 11vs. Logic Level VBIAS (V)CHARGE INJECTIOIN (pC)6420–2–4–6–15–10–510051504776-005 TA = 25C VDD = 15VVSS =–15V VDD = 12VVSS = 0V Figure 12. Charge Injection vs. Source Voltage TEMPERATURE (C)TIME (ns)220200180160140120100806040200––04020608010012004776-004 AOFF BON 12V SS BOFF AON 12V SS BOFF AON 15V DS AOFF BON 15V DS Figure 13TRANSITIONTimes vs. Temperature FREQUENCY (Hz)OFF ISOLATION (dB)0–100–90–80–70–60–50–40–30–20–1010k100k10M1M100M1G04776-010 VDD = 15VVSS =–15VTA = 25C Figure 14. Off Isolation vs. Frequency FREQUENCY (Hz)CROSSTALK (dB)0–100–90–80–70–60–50–40–30–20–1010k100k10M1M100M1G04776-008 VDD = 15VVSS =–15VTA = 25C BETWEENSA AND SB BETWEENS1 AND S2 Figure 15Crosstalk vs. Frequency Data Sheet ��Rev. | Page of FREQUENCY (Hz)ON RESPONSE (dB)0–30–10–5–15–20–2510k100k10M1M100M10G1G04776-009 VDD = 15VVSS =–15VTA = 25C Figure 16. On Response vs. Frequency FREQUENCY (Hz)THD + N (%)10.001.000.100.01101001k10k100k04776-019 LOAD = 10kTA = 25C VDD = 5V, VSS =–S = 3.5Vrms VDD = 15V, VSS =–S = 5Vrms Figure 17THD + N vs. Frequency VBIAS (V)CAPACITANCE (pF)543210–––10051504776-007 VDD = 15VVSS =–TA = 25C SOURCE/DRAIN ON SOURCE OFF Figure 18. Capacitance vs. Source Voltage for Dual Supply VBIAS (V)CAPACITANCE (pF)54312002410681204776-006 VDD = 12VVSS = 0VTA = 25C SOURCE/DRAIN ON SOURCE OFF Figure 19. Capacitance vs. Source Voltage for Single Supply Data Sheet ��Rev. | Page of OUTLINE DIMENSIONS 16981 PIN 1 SEATINGPLANE 8°0° 4.504.404.30 6.40BSC 5.105.004.900.65BSC0.150.05 1.20MAX0.200.09 0.750.600.45 0.300.19 COPLANARITY0.10COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 30. 16Lead Thin Shrink Small Outline Package [TSSOP]16)Dimensions shown in millimeters 1.451.30 SQ1.15111808-A 0.50BSCBOTOM VIEWTOP VIEW EXPOSEDPIN 1INDIC 3.103.00 SQ2.90 0.700.600.50 TINGPLANE 0.05 MAX0.02 NOM 0.20 REF0.25 MIN COPLANARITY0.08 PIN 1INDIC 0.300.230.18 COMPLIANTJEDEC STANDARDS MO-220-WEED. FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET. 0.800.750.70 Figure 31. 12Lead Lead Frame Chip Scale Package [LFCSP]3 mm × 3 mm Bodyand 0.75 mm Package Height(CP12Dimensions shown in millimetersORDERING GUIDEModelTemperature RangePackageDescriptionPackage Option ADG1236YRUZ40°C to +125°CLead Thin Shrink Small Outline Package [TSSOP] ADG1236YRUZREEL40°C to +125°CLead Thin Shrink Small Outline Package [TSSOP] ADG1236YRUZREEL740°C to +125°CLead ThiShrink Small Outline Package [TSSOP] ADG1236YCPZ500RL740°C to +125°C Lead Lead Frame Chip Scale Package [LFCSP] ADG1236YCPZREEL740°C to +125°C Lead Lead Frame Chip Scale Package [LFCSP] �� &#x/MCI; 35;&#x 000;&#x/MCI; 35;&#x 000;1 &#x/MCI; 36;&#x 000;&#x/MCI; 36;&#x 000;Z = RoHS Compliant Part. Data Sheet ��Rev. | Page of NOTES Data Sheet ��Rev. | Page of NOTES © 2005 – 2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.D047763/16(A) Low CapacitanceLowCharge Injection, ± 15 V /12 V i CMOS, Dual SPDT Switch Data Sheet ADG1236 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106,Norwood, MA 020629106, U.S.A.Tel: 781.329.470020052016Analog De Technical Support www.analog.com EATURES1.3 pF off capacitance3.5 pF capacitancepC charge injectionV supply rangeon resistanceFully pecified +12V, ±15upply requiredV logiccompatible inputsRailrail operationead TSSOPand 12lead LFCSP packagesTypical power consumption.03PPLICATIONSAutomatic test equipmentData acquisition systemsBattery ADG1236 D1D2S2BS2A Figure ENERAL DESCRIPTIONThe ADG1236is a monolithic CMOS device containing two independently selectable SPDT switches.It is designed on an CMOSprocess. CMOS (industrialCMOS) is a modular manufacturing process combining highvoltage complementary metaloxide semiconductorCMOSand bipolar technologies.It enables the development of a wide range of high performance analog ICs capable of 3V operation in a footprint that no previousgeneration of highvoltage devices has been able to achieve.Unlike analog ICs using conventional CMOS processes, Data Sheet ADG1236 Rev. A | Page 13 of 16 VOUT 50NETWORKANALYZER RL50 IN V INSAD VSVDDVSS 0.1FVDD 0.1FVSS GND 04776-02650 NCSBOFF ISOLATION = 20 logVOUTVS Figure 26. Test Circuit 7„Off Isolation VOUT 50NETWORKANALYZERRL50 IN VINSAD VSVDDVSS 0.1FVDD 0.1FVSS GND 04776-02750 NCSBINSERTION LOSS = 20 logVOUTWITH SWITCHVOUTWITHOUT SWITCH Figure 27. Test Circuit 8„Channel-to-Channel Crosstalk CHANNEL-TO-CHANNEL CROSSTALK = 20 logVOUTGNDSADSBVOUTNETWORKANALYZERRL50 R50 VSVS VDDVSS 0.1FVDD 0.1FVSS 04776-028IN Figure 28. Test Circuit 9„Bandwidth VOUT RSAUDIO PRECISION RL10k IN VINSD VSV p-pVDDVSS 0.1FVDD 0.1FVSS GND 04776-029 Figure 29. Test Circuit 10„THD + Noise ADG1236 Data Sheet Rev. A | Page 12 of 16 TEST CIRCUITS IDSSDVS 04776-020 V Figure 20. Test Circuit 1„On Resistance SD V S A A VD IS (OFF)ID (OFF)04776-021 Figure 21. Test Circuit 2„Off Resistance SD AVD ID (ON) NCNC = NO CONNECT Figure 22. Test Circuit 3„On Leakage INVOUT DSAVDDVSSVDDVSS GND CL35pF SB V INVS 0.1F 0.1F RL300 50%50%90%50%90%tONtOFF Figure 23. Test Circuit 4„Switching Times INVOUT DSAVDDVSSVDDVSS GND CL35pF SBVINVS 0.1F 0.1F RL300 80%tBBMtBBMVOUTVIN Figure 24. Test Circuit 5„Break-Before-Make Time Delay CLOSEDSWITCH) OFFVOUTONQINJ = CLVOUT 04776-025 INVOUT DSAVDDVSSVDDVSS GND CL1nF NC SB V IN VS 0.1F Figure 25. Test Circuit 6„Charge Injection Data Sheet ADG1236 Rev. A | Page 3 of 16 SPECIFICATIONS DUAL SUPPLY = 15 V ± 10%, V = Š15 V ± 10%, GND = 0 V, unless otherwise noted. Version Parameters 25°C Š40°C to +85°C Š40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to V V On Resistance (R120  typ V = ±10 V, I = Š1 mA; Figure 20 = +13.5 V, V = Š13.5 V On Resistance Match Between Channels (R3.5  typ V = ±10 V, I = Š1 mA 6 10 12  max On Resistance Flatness (RFLAT(ON)) 20  typ V = Š5 V, 0 V, +5 V; I 57 72 79  max LEAKAGE CURRENTS V = +16.5 V, V = Š16.5 V Source Off Leakage, I (Off) ±0.02 nA typ = ±10 V, V10 V; Figure 21 max Drain Off Leakage, I (Off) ±0.02 nA typ = ±10 V, V10 V; Figure 21 max Channel On Leakage, I (On) ±0.02 nA typ V = V = ±10 V; Figure 22 max DIGITAL INPUTS Input High Voltage, VINH V min Input Low Voltage, V V max Input Current, I0.005 µA typ V = VINL or VINH µA max Digital Input Capacitance, C 2 pF typ DYNAMIC CHARACTERISTICS Transition Time, tTRANSOFF 125 ns typ R = 35 pF = 10 V; Figure 23 Transition Time, tTRANSOFF 70 ns typ R = 35 pF = 10 V; Figure 23 Break-Before-Make Time Delay, t 25 ns typ R = 35 pF = V = 10 V; Figure 24 Charge Injection Š1 pC typ V = 0 V, R = 0 , C = 1 nF; Figure 25 Off Isolation 80 dB typ = 5 pF, f = 1 MHz; Figure 26 Channel-to-Channel Crosstalk 85 dB typ = 5 pF, f = 1 MHz; Figure 27 Total Harmonic Distortion + Noise 0.15 % typ = 10 k, 5 V rms, f = 20 Hz to 20 kHz 1000 MHz typ R = 5 pF; Figure 28 (Off) 1.3 pF typ f = 1 MHz; V = 0 V 1.6 pF max f = 1 MHz; V = 0 V (On) 3.5 pF typ f = 1 MHz; V = 0 V 4.3 pF max f = 1 MHz; V = 0 V Data Sheet ADG1236 Rev. A | Page 7 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN1GNDS2BS2AIN204776-002 NC = NO CONNECT. DO NOT CONNECT T O THIS PIN. ADG1236TOP VIEW(Not to Scale)Figure 2. TSSOP Pin Configuration NOTES1.NC = NO CONNECT. DO NOT CONNECTTO THIS PIN.2. THE EXPOSED PAD MUST BE TIED TO SUBSTRATE, V 04776-003S2BS1B ADG1236TOP VIEW(Not to Scale)Figure 3. LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description IN1 Logic Control Input. S1A Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. S1B Source Terminal. Can be an input or output. Most Negative Power Supply Potential. 6 4 GND Ground V) Reference. 7, 8, 14 to 16 10 No Connect. 9 5 IN2 Logic Control Input. S2A Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. S2B Source Terminal. Can be an input or output. 13 9 VMost Positive Power Supply Potential. ADG1236 Data Sheet Rev. A | Page 2 of 16 TABLE OF CONTENTS Features .............................................................................................. 1Applications ....................................................................................... 1Functional Block Diagram .............................................................. 1General Description ......................................................................... 1Product Highlights ........................................................................... 1Revision History ............................................................................... 2Specifications ..................................................................................... 3Dual Supply ................................................................................... 3Single Supply ................................................................................. 5Absolute Maximum Ratings ............................................................6ESD Caution...................................................................................6Truth Table for Switches ...............................................................6Pin Configurations and Function Descriptions ............................7Terminology .......................................................................................8Typical Performance Characteristics ..............................................9Test Circuits ..................................................................................... 12Outline Dimensions ....................................................................... 14Ordering Guide .......................................................................... 14REVISION HISTORY 3/16„Rev. 0 to Rev. A Changes to Figure 2 and Figure 3 ................................................... 7 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 9/05„Revision 0: Initial Version