IFIC CSIC Universidad de Valencia MULTIBOOT AND SPI FLASH MEMORY 1 l MULTIBOOT Status VHDL reconfiguration Integrate as Wishbone slave Create libraries and driver ID: 444284
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Slide1
25 Sept. 2013
IFIC (CSIC – Universidad de Valencia)
MULTIBOOT AND
SPI FLASH MEMORY
1Slide2
l
MULTIBOOT: Status
VHDL
reconfiguration
Integrate as Wishbone
slave
Create
libraries
and driver Slow control using embedded software Write the multiboot images in flash memory using LM32
2Slide3
SPI INTERFACE: LM32
Wishbone
slave
Rx_mac2buf
I2C
Fifo
31 TDCs
TDC0
Management
& Control
Data
Control
Wishbone bus
RxPacket
Buffer
64KB
IP/UDP Packet Buffer
Stream Selector (IPMUX)
Rx_buf2data
RxPort 1
RxPort 2
RxPort_m
Management
& Config.
Tx_pkt2mac
Tx_data2buf
TxPort 1
TxPort 2
TxPort_m
Flags
Rx Stream Select
TxPacket
Buffer
32KB
Flags
Tx Stream Select
31 PMTs
UTC time &
Clock (PPS, 125 MHz)
Pause
Frame
ADC
Management
& Control
Hydrophone
Fifo
TDC
30
Fifo
Nano
Beacon
GPIO
Debug LEDs
I2C
Debug RS232
Temp
Compass
Tilt
Point to Point interconnection
Xilinx
Kintex-7
Start Time Slice UTC &
Offset counter since
Time Slice Start
MEM
S
2
nd
CPU
LM32
M
M
WB Crossbar
(1x8)
WB Crossbar
(3x2)
S
M
S
M
M
S
S
M
M
M
S
S
S
UART
S
M
M
S
M
M
State Machine
SPI
S
M
SPI
Flash
Multiboot
Management
& Control
M
S
S
3Slide4
l
SPI FLASH: MEMORY MAP
KC705 EV.
BOARD
CLBv2
Flash Memory
N25Q128 (16 Mbytes
)N25Q1Gb (128 Mbytes)
Sectors
256 (64
Kbytes
each)2048 (64 Kbytes each)Pages65536 (256 bytes each)524288 (256 bytes each) First approach using SPI flash memory available in Kintex 7 Evaluation board CLBv2 flash memory:
larger but
with similar command
set
4Slide5
l
CLBv2 SPI FLASH : MEMORY MAP
Golden
Image
Multiboot
Image 1
Free
Space
Base
Address
Stable
Image to start up and recovery the systemDiferent Images to reconfigure the system
Space
available in SPI flash memory
5
Multiboot
Image
2
Multiboot
Image
3
Conf.Parameters
16
Mbytes
16
Mbytes
16
Mbytes
16
Mbytes
16
Mbytes
48
Mbytes
Configuration
parametersSlide6
l
LM32 WB SLAVE: SPI DRIVER
6
spi_clock
WISHBONE BUS
WISHBONE INTERFACE
SERIAL
INTERFACE
CLOCK GENERATOR
STARTUP
PRIMITIVE
SPI DRIVER
miso
mosi
slave
enable
SPI
Opencores
:
From
the
WR
repository
Slide7
l
LM32 WB SLAVE: SPI PROTOCOL
7
Slave
Memory Enable
SPI clock
Data to memory
(MOSI)Data
from
memory
(MISO)
SPI PROTOCOL: 4 signalsSlave Enable (Memory is selected by driving this signal low)SPI clockMOSI (Master Out Slave In) Data from LM32 to flash memory
MISO (Master In Slave Out
) Data from flash memory to
LM32Slide8
l
LM32 WB SLAVE: SLOW CONTROL
Read
Identification
Sector Erase
Bulk EraseWrite
status register
Read Status register
Write
enable
Write
disbalePage programRead8Library functions implemented:SUCCESSFUL TEST!Slide9
l
FLASH PROGRAMMING CHAIN
Storage Module
Flash
memory
Driver
SPI
Driver
Slow
Control
Module
T
o create
the new programming
chain (
proposed by
Vincent)
Check
the
spi
driver in
the
new
embedded
software (
modifiy
if
needed
)
9Slide10
l
FLASH PROGRAMMING TEST
Create
firmware (HEX or BIN)
File
MCS file
contain information
about
address
and checksum (maybe not needed)Send firmware file to FPGA over serial link (UART Communication)Store it in flash memory using LM32-SPI
slow control
Reboot
FPGA using multiboot
slow control
10