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COE 202: Digital Logic Design COE 202: Digital Logic Design

COE 202: Digital Logic Design - PowerPoint Presentation

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COE 202: Digital Logic Design - PPT Presentation

Combinational Circuits Part 3 KFUPM Courtesy of Dr Ahmad Almulhem Objectives Decoders Encoders Multiplexers DeMultiplexers KFUPM Functional Blocks Digital systems consists of many components blocks ID: 257598

decoder kfupm encoder mux kfupm decoder mux encoder inputs output select outputs input lines 2x1 table truth equations s0s1

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Slide1

COE 202: Digital Logic DesignCombinational CircuitsPart 3

KFUPM

Courtesy of Dr. Ahmad

AlmulhemSlide2

ObjectivesDecodersEncodersMultiplexersDeMultiplexersKFUPMSlide3

Functional BlocksDigital systems consists of many components (blocks)Useful blocks needed in many designsArithmetic blocksDecodersEncodersMultiplexers KFUPM

iPhone motherboard (torontophonerepair.com)Slide4

Functional BlocksDigital systems consists of many components (blocks)Useful blocks needed in many designsArithmetic blocksDecodersEncodersMultiplexers KFUPM

iPhone motherboard (torontophonerepair.com)

Examples

of

MSI devicesSlide5

DecoderInformation is represented by binary codesDecoding - the conversion of an n-bit input code to an m-bit output code with n <= m <= 2n such that each valid code word produces a unique output codeCircuits that perform decoding are called decoders

A decoder is a minterm generator

KFUPM

.

.

.

.

n

inputs

2

n

outputs

n-to-2

n

DecoderSlide6

Decoder (Uses)Decode a 3-bit op-codes:Home automation:KFUPM

3-to-8

Decoder

Add

Sub

And

Xor

Not

Load

Store

Jump

op0

op1

op2

2-to-4

Decoder

Light

A/C

Door

Light-A/C

C

0

C

1

Load a

Add b

Store c

.

.Slide7

Decoder with EnableKFUPMA decoder can have an additional input signal called the enable which enables or disables the output generated by the decoder

.

.

.

2

n

outputs

n-to-2

n

Decoder

Enable bit

.

n

inputsSlide8

2-to-4 DecoderA 2-to-4 Decoder2 inputs (A1, A0)22 = 4 outputs (D3, D2, D1, D0)

KFUPMSlide9

2-to-4 DecoderA 2-to-4 Decoder2 inputs (A1, A0)22 = 4 outputs (D3, D2, D1, D0)

Truth Table

A

1

A

0

D

0

D

1

D

2

D

3

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

1

0

0

0

1

KFUPMSlide10

2-to-4 DecoderA 2-to-4 Decoder2 inputs (A1, A0)22 = 4 outputs (D3, D2, D1, D0)

Truth Table

A

1

A

0

D

0

D

1

D

2

D

3

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

1

0

0

0

1

Src: Mano’s book

KFUPMSlide11

2-to-4 Decoder with EnableKFUPMEN

A

1

A

0

D

0

D

1

D

2

D

3

0

X

X

0

0

0

0

1

0

0

1

0

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

0

0

1

Truth TableSlide12

2-to-4 Decoder with EnableKFUPMEN

A

1

A

0

D

0

D

1

D

2

D

3

0

X

X

0

0

0

0

1

0

0

1

0

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

0

0

1

Src: Mano’s book

Truth TableSlide13

3-to-8 DecoderKFUPM3-to-8 Decoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2Slide14

3-to-8 DecoderKFUPMA2

A

1

A

0

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

0

1

0

0

1

1

0

0

0

0

0

0

0

1

0

1

1

1

0

0

0

0

0

0

0

1

3-to-8

Decoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2Slide15

3-to-8 DecoderKFUPM3-to-8 Decoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2Slide16

3-to-8 Decoder (using 2 2-to-4 decoders)KFUPM3-to-8 Decoder

2-to-4

Decoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

2-to-4

Decoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

0

A

1

A

2

E

ESlide17

Decoder-Based Combinational CircuitsA Decoder generates all the mintermsA boolean function can be expressed as a sum of mintermsAny boolean function can be implemented using a decoder and an OR gate. Note: The Boolean function must be represented as minterms (not minimized form)KFUPMSlide18

Decoder-Based Combinational Circuits (Example)KFUPMX

Y

Z

C

S

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

S = ∑m (1,2,4,7)

C = ∑m (3,5,6,7)

3 inputs and 8 possible minterms

3-to-8 decoder can be used for implementing this circuitSlide19

Decoder-Based Combinational Circuits (Example)KFUPMSrc: Mano’s book

X

Y

Z

C

S

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

S = ∑m (1,2,4,7)

C = ∑m (3,5,6,7)

3 inputs and 8 possible minterms

3-to-8 decoder can be used for implementing this circuitSlide20

Decoder-Based Combinational Circuits (Summary)Good if:Many output functions with same inputsEach output has few mintermsHint:Check if the function complement has fewer minterms and use NOR instead of OR.KFUPMSlide21

EncoderEncoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n £ m £ 2

n such that each valid code word produces a unique output code

Circuits that perform encoding are called

encoders

An encoder has 2

n

(or fewer) input lines and

n

output lines which generate the binary code corresponding to the input values

Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.

.

.

.

.

n

outputs

2

n

inputs

2

n

-to-n

Encoder

KFUPMSlide22

8-to-3 EncoderDescription:23 = 8 inputs, 3 outputsone input =1, others = 0’sEach input generate unique binary codeKFUPM

8-to-3

Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2Slide23

8-to-3 Encoder (truth table)KFUPM8-to-3 Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1Slide24

8-to-3 Encoder (truth table)KFUPM8-to-3 Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

1

0

0

0

0

0

0

0

0

0

0

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1Slide25

8-to-3 Encoder (truth table)KFUPM8-to-3 Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

0

1

0

0

0

0

0

0

1

0

0

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1Slide26

8-to-3 Encoder (truth table)KFUPM8-to-3Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

0

0

0

0

0

1

0

0

1

0

1

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1Slide27

8-to-3 Encoder (truth table)KFUPM8-to-3Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

0

0

0

0

0

0

0

1

1

1

1

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1Slide28

8-to-3 Encoder (equations)KFUPM8-to-3Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1

Note: This truth table is not complete! Why?

Output equations:

A

0

= ?

A

1

= ?

A

2

= ?Slide29

8-to-3 Encoder (equations)KFUPM8-to-3Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1

Output equations:

A

0

= D

1

+ D

3

+ D

5

+ D

7

A

1

= ?

A

2

= ?Slide30

8-to-3 Encoder (equations)KFUPM8-to-3Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1

Output equations:

A

0

= D

1

+ D

3

+ D

5

+ D

7

A

1

= D

2

+ D

3

+ D

6

+ D

7

A

2

= ?Slide31

8-to-3 Encoder (equations)KFUPM8-to-3Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1

Output equations:

A

0

= D

1

+ D

3

+ D

5

+ D

7

A

1

= D

2

+ D

3

+ D

6

+ D

7

A

2

= D

4

+ D

5

+ D

6

+ D

7Slide32

8-to-3 Encoder (circuit)KFUPM8-to-3Encoder

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

A

0

A

1

A

2

Output equations:

A

0

= D

1

+ D

3

+ D

5

+ D

7

A

1

= D

2

+ D

3

+ D

6

+ D

7

A

2

= D

4

+ D

5

+ D

6

+ D

7

A

0

A

1

A

2

D

1

D

3

D

5

D

7

D

2

D

3

D

6

D

7

D

4

D

5

D

6

D

7Slide33

8-to-3 Encoder (limitations)KFUPMOutput equations:A0 = D1 + D3 + D5 + D7A1 = D

2 + D3 + D6 + D7

A

2

= D

4

+ D

5

+ D

6

+ D

7

inputs

outputs

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

2

A

1

A

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

1

1

1

Two Limitations:

1. Two or more inputs = 1

Example: D

3

= D

6

= 1

A

2

A

1

A

0

= 111

All inputs = 0

Same as D

0

=1Slide34

Priority EncoderAddress the previous two limitationsTwo or more inputs = 1Consider the bit with highest priorityAll inputs = 0Add another output v to indicate this combinationKFUPMSlide35

4-to-2 Priority EncoderKFUPMDescription: 22 = 4 inputs, 2 + 1 outputs Two or more 1’s take highest prioritySlide36

4-to-2 Priority EncoderKFUPMinputs

outputs

D

3

D

2

D

1

D

0

A

1

A

0

V

0

0

0

0

X

X

0

0

0

0

1

0

0

1

0

0

1

X

0

1

1

0

1

X

X

1

0

1

1

X

X

X

1

1

1

Description:

2

2

= 4 inputs, 2 + 1 outputs

Two or more 1’s take highest

priority

This is a condensed truth table!

It has only 5 rows instead of 16!

Row 3 = 2 combinations

Row 4 = 4 combinations

Row 5 = 8 combinationsSlide37

4-to-2 Priority EncoderKFUPMinputs

outputs

D

3

D

2

D

1

D

0

A

1

A

0

V

0

0

0

0

X

X

0

0

0

0

1

0

0

1

0

0

1

X

0

1

1

0

1

X

X

1

0

1

1

X

X

X

1

1

1

Description:

2

2

= 4 inputs, 2 + 1 outputs

Two or more 1’s take highest

prioritySlide38

4-to-2 Priority EncoderKFUPMinputs

outputs

D

3

D

2

D

1

D

0

A

1

A

0

V

0

0

0

0

X

X

0

0

0

0

1

0

0

1

0

0

1

X

0

1

1

0

1

X

X

1

0

1

1

X

X

X

1

1

1

Description:

2

2

= 4 inputs, 2 + 1 outputs

Two or more 1’s take highest

priority

Equations:

A

0

= D

3

+ D

1

D

2

A

1

= D

2

+ D

3

V = D

0

+ D

1

+ D

2

+ D

3Slide39

4-to-2 Priority EncoderKFUPMinputs

outputs

D

3

D

2

D

1

D

0

A

1

A

0

V

0

0

0

0

X

X

0

0

0

0

1

0

0

1

0

0

1

X

0

1

1

0

1

X

X

1

0

1

1

X

X

X

1

1

1

Description:

2

2

= 4 inputs, 2 + 1 outputs

Two or more 1’s take highest

priority

Equations:

A

0

= D

3

+ D

1

D

2

A

1

= D

2

+ D

3

V = D

0

+ D

1

+ D

2

+ D

3Slide40

MultiplexersA combinational circuitHas a single outputDirects one of 2n input to the outputChoosing which input is done using n select linesKFUPM

2

n

inputs

n select lines

one output

2

n

x 1

MUXSlide41

2x1 MUXA 2x1 multiplexer (MUX) has 2 inputs, 1 output and 1 select lineY=D

0 for S0=0, and Y=D1

for S

0

=1

Minimizing will result in: Y = S

0

’.D

0

+ S

0

.D

1

Exercise

: Draw the circuit?

KFUPM

S

0

D

0

D

1

Y

2x1 MUXSlide42

2x1 MUXA 2x1 multiplexer (MUX) has 2 inputs, 1 output and 1 select lineY=D0

for S0=0, and Y=D1 for S

0

=1

Minimizing will result in: Y = S

0

’.D

0

+ S

0

.D

1

Exercise

: Draw the circuit?

KFUPM

S

0

D

0

D

1

Y

2x1 MUXSlide43

4x1 MUXA 4x1 MUX has 4 input lines (D0, D1, D2, D3) , 1 output Y, and 2 Select Lines (S0, S1)The output for different select values is defined as:

S0S1 = 00, Y = D

0

S

0

S

1

= 01, Y = D

1

S

0

S

1

= 10, Y = D

2

S

0S

1

= 11, Y = D

3

Y = S

1

S

0

D0 + S1S0

D1 + S1S0D

2 + S1S0D

3 The output Y depends on the minterms of the Select lines

Exercise: Draw the circuit?

KFUPM

S

1

S

0

D

0

D

1

D

2

D

3

Y

4x1 MUXSlide44

4x1 MUXA 4x1 MUX has 4 input lines (D0, D1, D2, D3) , 1 output Y, and 2 Select Lines (S0, S1)The output for different select values is defined as:

S0S1 = 00, Y = D

0

S

0

S

1

= 01, Y = D

1

S

0

S

1

= 10, Y = D

2

S

0S

1

= 11, Y = D

3

Y = S

1

S

0

D0 + S1S0

D1 + S1S0D

2 + S1S0D

3 The output Y depends on the minterms of the Select lines

Exercise: Draw the circuit?

KFUPM

S

1

S

0

D

0

D

1

D

2

D

3

Y

4x1 MUXSlide45

Quad 2x1 MUXA MUX for two 4-bit numbers.Has a 4-bit output and a single select lineY = A If S0 = 0Y = B if S0 = 1

KFUPM

S

0

A

0

A

1

A

2

A

3

B

0

B

1

B

2

B

3

Y

0

Y

1

Y

2

Y

3

QUAD

2X1

MUXSlide46

Quad 2x1 MUXCan be built using four 2x1 MUXesKFUPM

S

0

A

0

B

0

Y

0

2x1 MUX

S

0

A

2

B

2

Y

2

2x1 MUX

S

0

A

1

B

1

Y

1

2x1 MUX

S

0

A

3

B

3

Y

3

2x1 MUXSlide47

MUX-based DesignA MUX can be used to implement any function expressed using its mintermsExample: Implement F(A,B,C)=∑(1,2,6,7) using MUXesSolution1: We can use a MUX with the number of select lines equal to the number of input variables of the function. Since this function has 3 input variables, it will require 3 select lines, i.e. an 8x1 MUX

KFUPMSlide48

MUX-based Design (n-Select lines)KFUPMF(A,B,C)=∑(1,2,6,7)A

B

C

F

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

1Slide49

MUX-based Design (n-Select lines)KFUPM

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

S

0

S

2

S

1

F(A,B,C)=∑(1,2,6,7)

A

B

C

F

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

1Slide50

MUX-based Design (n-Select lines)KFUPM

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

F

0

1

1

0

0

0

1

1

S

0

S

2

S

1

A B C

F(A,B,C)=∑(1,2,6,7)

A

B

C

F

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

1Slide51

MUX-based Design (n-1 Select lines)Implement the function F(A,B,C) =∑(1,2,6,7) We will use 2 select lines instead of the 3 required for the three input variablesA  S1, B  S0

The third variable C and its complement will serve as two of the inputs to the MUX

KFUPMSlide52

MUX-based Design (n-1 Select lines)KFUPMA

B

C

F

0

0

0

0

F = C

0

0

1

1

0

1

0

1

F = C’

0

1

1

0

1

0

0

0

F = 0

1

0

1

0

1

1

0

1

F = 1

1

1

1

1

D

0

D

1

D

2

D

3

F

S

1

S

0

A B

C

C’

0

1

F(A,B,C)=∑(1,2,6,7)Slide53

Example 2Implement the function F(A,B,C,D)=∑(1,3,4,11,12,13,14,15) We can implement this function with 3 Select lines => an 8x1 MUX is requiredKFUPMSlide54

Example 2 (cont.)KFUPMA

B

C

D

F

0

0

0

0

0

F = D

0

0

0

1

1

0

0

1

0

0

F = D

0

0

1

1

1

0

1

0

0

1

F = D’

0

1

0

1

0

0

1

1

0

0

F = 0

0

1

1

1

0

1

0

0

0

0

F = 0

1

0

0

1

0

1

0

1

0

0

F = D

1

0

1

1

1

1

1

0

0

1

F = 1

1

1

0

1

1

1

1

1

0

1

F = 1

1

1

1

1

1

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

1

8x1

MUX

F

A B C

S

2

S

1

S

0

F(A,B,C,D)=∑(1,3,4,11,12,13,14,15) Slide55

DeMultiplexerPerforms the inverse operation of a MUXIt has one input and 2n outputsThe input is passed to one of the outputs based on the n select lineKFUPM

2

n

outputs

n select lines

one input

1 x 2

n

DeMUXSlide56

1x2 DeMUXKFUPMThe circuit has an input E, the outputs are given by: D0 = E, if S=0 D0 = S E D1 = E, if S=1 D1 = S E

S

E

1 x 2 DeMUX

D

0

D

1Slide57

1x4 DeMUXThe circuit has an input E, the outputs are given by: D0 = E, if S0S1=00 D0 = S1’S0’ E D1 = E, if S

0S1=01 D1

= S

1

’S

0

E

D

2

= E, if S

0

S

1

=10 D

2

= S

1S0’ E

D

3

= E, if S

0

S

1

=11 D3 = S1S

0 E

KFUPM

E

S

1

S

0

D

0

D

1

D

2

D

3

1 x 4 DeMUXSlide58

DeMUX vs DecoderA 1x4 DeMUX is equivalent to a 2x4 Decoder with an EnableThink of S1S0 a the decoder’s inputThink of E as the decoder’s enableIn general, a DeMux

is equivalent to a Decoder with an Enable

KFUPM

E

D

0

D

1

D

2

D

3

1 x 4 DeMUX

S

1

S

0Slide59

DeMUX vs DecoderKFUPMEN

A

1

A

0

D

0

D

1

D

2

D

3

0

X

X

0

0

0

0

1

0

0

1

0

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

0

0

1

Src: Mano’s book

2x4 Decoder Truth TableSlide60

DeMUX vs DecoderKFUPMEN

A

1

A

0

D

0

D

1

D

2

D

3

0

X

X

0

0

0

0

1

0

0

1

0

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

0

0

1

Src: Mano’s book

2x4 Decoder Truth Table

To convert a 2x4 Decoder with an Enable to a 1x4

DeMux

:

Assign

DeMux’s

input (actual data) to EN

Assign

DeMux’s

selection lines (S

1

,S

0

) to the inputs A

1

, A

0

Data/

S

1

/

S

0

/Slide61

SummaryUseful Functional BlocksDecodersEncodersMultiplexersDeMultiplexersAll are examples of MSI devicesCan be used to build bigger systemsKFUPM