EssentialVHDLforASICsConcurrent Statements - GENERATEVHDL provides the - PDF document

EssentialVHDLforASICsConcurrent Statements - GENERATEVHDL provides the GENERATE statement to create well-patterned structures easily.Any VHDL concurrent statement can be included in aGENERATE statement, including another GENERATETwo ways to applyFOR Scheme Format: EssentialVHDLforASICsWith the FOR schemeAll objects created are similar.The GENERATE parameter must be discrete and is undeÞnedoutside the GENERATE statement.Note: This structure could have been created by:provided the AND operator was overloaded for vector operations. sig1(7:0)sig2(7:0)sig3(7:0) EssentialVHDLforASICsAllows for conditional creation of components.IF Scheme Format:ormat:The next slide will show how we can use both FOR and IF EssentialVHDLforASICsUse of GENERATE - An exampleSuppose we want to build an 8-bit shift register.SupposefurthermorethatwehadpreviouslydeÞnedthefollowing DCLKQE DCLKQE DCLKQE DCLKQE d(1)d(2)q(1)q(2) d(7)q(7) EssentialVHDLforASICsUsing GENERATEFromtheblockdiagramweknowwhattheentityshouldlooklike.Within the architecture statement we have to declare thecomponentswithinthedeclarationregionbeforeusingthem.Thisis done as follows:Component declarations look just like entity clauses, exceptCOMPONENT replaces ENTITY. Use cut and paste to preventmistakes! EssentialVHDLforASICsAfter the component declarations, we declare the internal signal.With loop and generate statements, instantiate muxes and dffÕs. EssentialVHDLforASICsConcurrent Statements - ASSERTTheassertionstatementchecksaconditionandreportsamessagewith a severity level if the condition is Format:Severity levels are:Note - general informationWarning - undesirable conditionError - task completed, result wrongFailure - task not completedSimulators stop when the severity level matches or exceeds thespeciÞed severity level.Simulators generally default to a severity level of ÒfailureÓ EssentialVHDLforASICsconcurrent statement areassequential statement areasstatement area of entity declaration Remember, the ASSERT statement triggers when the speciÞed EssentialVHDLforASICsConcurrent Statements - Process StatementThe PROCESS statement encloses a set ofsequentially executedstatements. Statements within the process are executed in theordertheyarewritten.However,whenviewedfromtheÒoutsideÓfrom the ÒoutsideÓ, a process is a single concurrent statement.Format:ormat:Example:ARCHITECTURE example OF nand_gate IS BEGIN nand_gate: PROCESS (a,b) BEGIN IF a = Ô1Õ AND b = Ô1Õ THEN z ÔÕ ELSE z ÔÕ END IF; END PROCESS nand_gate;Why use a process? Some behavior is easier and more natural todescribe in a sequential manner. The next state decoder in a state EssentialVHDLforASICsProcess Sensitivity ListThe processprocess statement to be executed.transitiononofthesignalsinthesignalsensitivitylistwillcause the process to execute.Signals to put in the sensitivity list:Signals used in conditional expressionsWhat happens if a signal is left out of the sensitivity list?What does the synthesis tool do with the sensitivity list?Avoid problems with sensitivity list omissions by compiling with ÒsythesischeckÓ on. Like this: EssentialVHDLforASICsNote that so far we havenÕt mentioned delay. Why not?Both propagation delay and wiring delay is a real-world problem that must beeventually dealt with. However, at the model creation stage, it is helpful to nothave to consider delay. Instead, the emphasis is to create correct functionalbehavior.However, this does not mean the designer can go about designing with noconcernaboutdelay.WhenwritingHDLcode,youmusthaveaverygoodideawhat the structure you are creating will look like in a schematic sense.Otherwise, the synthesized circuit may have excessive delays, preventing itsVHDL does have statements for representing several different kinds of delay.However, when describing a circuit to be synthesized, we never use thembeen proven correct. When real delays are inserted into your design (this isdone automatically) often a whole world of problems crop up.The basic idea is to make a model work, and then make it work at the desiredspeed. Only experience will help you determine how fast your HDL code willeventually run. EssentialVHDLforASICsDelay TypesVHDLsignalassignmentstatementsprescribeanamountoftimethat must transpire before a signal assumes its new value.This prescribed delay can be in one of three forms:Transport:the default if no delay time is explicitly speciÞedscheduling for a future value to beSignals maintain their original value until the time for thescheduled update to occur. Any signal assignment will incur a delay of one of the three typesabove. inputoutput EssentialVHDLforASICsDelay Types - TransportDelay must be explicitly speciÞed by the user by the keywordTRANSPORT.The signal will assume the new value after speciÞed delay.Transport delay is like a inÞnite bandwidth transmission line. 51015202530354045 EssentialVHDLforASICsDelay Types - Inertialthe ÒAFTERÓ clause.Inertial delay provides for speciÞcation of input pulse width, i.e.ÔinertiaÕ of output, and propagation delay.Format:target[REJECTtime_expr]INERTIALwaveformWhen not used, the REJECT clause defaults to the value of theInertial delay acts like a real gate. It ÒeatsÓ pulses narrower inwidth than the propagation delay. 51015202530354045 EssentialVHDLforASICsDelay Types - InertialExample of gate with ÒinertiaÓ smaller than propagation delay:This shows a buffer that has a prop delay of 10ns, but passes pulses greaterREJECT can be used only with the keyword INERTIAL. 51015202530354045 EssentialVHDLforASICsDelay Types - Delta Delay is the signal assignment propagation delay if none isexplicitly prescribed.A delta time is an inÞnitesimal, but quantized unit of time. inÞnite number of delta times equals zer Thedeltadelaymechanismprovidesaminimumdelaysothatthesimulation cycle can operate correctly when no delays are statedexplicitly. That is:all active processes to execute in the same simulation cycleeach active process will suspend at somewaitwhen all processes are suspended, simulation is advanced theminimum time step necessary so that some signals can take ontheir new valuesprocesses then determine if the new signal values satisfy theconditions to proceed again from the wait condition EssentialVHDLforASICsStatements within processes are executed in the order in whichthey are written.The sequential statements we will look at are:Variable AssignmentReturn StatementProcedure Call*Have both a sequential and concurrent form. EssentialVHDLforASICsVariable Declaration and AssignmentVariables can be used only within sequential areas.Format:ormat:Example:VARIABLE spam : std_logic := Ô0Õ;ARCHITECTURE example OF funny_gate ISSIGNAL c : STD_LOGIC; BEGIN funny: PROCESS (a,b,c) VARIABLE temp : std_logic; BEGIN temp := a AND b; z END PROCESS funny; END ARCHITECTURE example;Variables assume value instantly.Variables simulate more quickly since they have no timeRemember, variables and signals have different assignment EssentialVHDLforASICsProvides conditional control of sequential statements.Condition in statement must evaluate to a Boolean value.Statements execute if boolean evaluates to TRUE.Formats: EssentialVHDLforASICs EssentialVHDLforASICsSynthesized example from previous page EssentialVHDLforASICsThe if statement implies a priority in how signals are assigned to the logicsynthesized. See the code segment below and the synthesized gates.NotehowsignalwiththesmallestgatedelaythroughthelogicwastheÞrstonelisted. You can use such behavior to your advantage. Note that use ofexcessively nested statements can yield logic with lots of gate delay.Beyond about four levels ofyield a faster implementation of the circuit. what are the delays for each path? EssentialVHDLforASICsArea and delay of nested IF statementWecanputreportingstatementsinoursynthesisscripttotellusthenumberofgate equivalents and the delays through all the paths in the circuit. For thisexample, we included the two statements: has the delay information: EssentialVHDLforASICsThe order in which the IFÕs conditional statement are evaluated also makes adifference in how the outputs value is assigned. For example, the Þrst check isfor (a = Ô1Õ). If this statement evaluates true, the output vegetable is assignedÒpotatoÓ for any input combination where a= Ô1Õ.If the Þrst check fails, the possibilities narrow. If the second check (b= Ô1Õ) istrue, then any combination where a is Ô0Õ an b is Ô1Õ will assign carrot tovegetable.If all prior checks fail, an ending ELSE catches all other possibilities. EssentialVHDLforASICsThe IF statement uses relational operators extensively.Relational operators return Boolean values (true, false) as theirresult. Operator =equal/=not equalless thanless than or equal&#x=-98;嘀greater than&#x=-98;嘀=greater than or equalThe expression for signal assignment and less than or equal arethe same. They are distinguished by the usage context.