Olivier Bourrion Rachid Guernane Damien Tourres Outline Design proposal Prototype for radiation test Triggering options Prototype Conclusion 2 04022020 FOCAL meeting Design proposal ID: 1010706
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1. Pad readout design Fatah RARBIOlivier Bourrion, Rachid Guernane, Damien Tourres
2. OutlineDesign proposalPrototype for radiation testTriggering optionsPrototype Conclusion204/02/2020FOCAL meeting
3. Design proposalPad Layer board is based in HGCROC: designed by OMEGA-IN2P3 for HGCAL in CMSWill be used as isAggregator Board gathers data and trigger information from pad layer boardBased in FPGACan generate Local-L1 trigger from Trigger info provided by HGCROC To be defined if needed in FoCAL04/02/2020FOCAL meeting3
4. Prototype FOR radiation test1 PCB (9 cm x8 cm) for single pad sensor: internal testing board15 PCB (9 cm x8 cm) for single pad sensor with dedicated connectors (TBD)3 PCB (45 cm x8 cm) for pad layer with dedicated connectors (TBD)1 PCB for interface board: final version (4 connections)1 PCB for interface board: demonstrator version (15 connections)2 PCB for Aggregator boardAggregator boardinterface board demonstratorinterface board “Final”Pad layer boardSingle Pad board04/02/2020FOCAL meeting4
5. Triggering and I/O number04/02/2020FOCAL meeting5Geometry 1: 1x1 cm²Geometry 2: 0.8x0.8 cm²Self TriggerExternal TriggerSelf TriggerExternal TriggerLocal AggregatorLocal TowerLocal AggredatorLocal TowerTotal I/O per HGCROC8 + 108 + 104 + 108 + 108 + 104 + 10#HGCROC per pad layer555888Total I/O per pad layer40 + 3440 + 3420 + 3464 + 5264 + 5232 + 52Total I/O per aggregation option 3x120 + 94120 + 9460 + 94192 + 194192 + 19496 + 194Total I/O per aggregation option 4x160 + 96160 + 9680 + 96256 + 258256 + 258128 + 258Total I/O per aggregation option 5x200 + 96200 + 96100 + 96320 + 402320 + 402160 + 402High-speed I/O + standard I/OHP = High Performance (speed @1.28Gb/s), 1.0 – 1.2VHR = High Range 1.2 – 3.3VStandard I/O shared when possible
6. Single Pad boardDesign of a single pad board and Interface board for geometry 1x1cm² pixel sizeIf geometry 0.8x0.8cm² number of channel x2 (140 in this case: means 2 HGCROC per single pad board)With hole to be connected through wire bonding to pad sensorHoles of 4mm down to 2mmProvide HV to pad sensor: TBD? 04/02/2020FOCAL meeting6
7. Testing BoardDesign of a testing board To emulate injection chargeTo be connected to single pad board with connectors (Spring-Loaded Contacts)Characterization with external Pulse generator Production test with automatic pulse generation (DAC)04/02/2020FOCAL meeting7
8. Focal Schedule @lpSC04/02/2020FOCAL meeting8Due to Covid-19 containment in France HGCROC Understanding: Define both firmware and software to get used to operate the HGCROC chipSingle Pad Board Design: Define the design of a development kit including ONE HGCROC and all other components as power supply, probes and holes to connect Si-pad sensor through wire bonding This PCB can be connected to the KCU105 through Interface board to be designed tooTesting Board Design: Emulate injection charge and permit to fully characterize both single pad board and pad layer board with external pulse generator or automatic pulse generation with DACLab Characterization and Test with pad sensor: Analyzing FEE board: noise, crosstalk, … Different Si-pad sensor could be tested Pad layer board Design: Define the design of the full FEE pad layer including the FIVE HGCROCAggregator Board: Define the design of the aggregator board to be linked to the FEE PAD Layer (prototype 1) and includes FPGA and optical link
9. ConclusionsIllustration of the full electronic design @LPSCPrototype design based on 1x1 cm² pixel geometry pad sensor of 9x8 cm²Difficult to design for 2 different geometry Time consuming and manpower!Geometry has to be definedTriggering options presented and the impact in the gathering possibilitiesCooling is not considered here:How is it done? (CALICE collaboration)What about the MAPS layer during the radiation test phase? It will have an impact in the proposed tower architecture: connection between the several PCB (single pad board, interface board demonstrator04/02/2020FOCAL meeting9
10. Back-up
11. Pad-layer:Proposed FEE architectureFEE architecture : PCB of 8 x 45 cm2 with 5 embedded “HGCROC”Analog signals from each pad sensors (72 pixels) will be read out by the HGCROC front-end chip which includes a charge sensitive amplifier-shaper and digitized to ship the data on a standard digital connectionProbes: TemperatureAnalog Power consumption Digital Power consumption Local power converter for cleaning power supplies1104/02/2020FOCAL meetingTrigger info. link Data link Local-L1-Trigger I2Cpower supply Probes
12. Pad-layer Design12few mm of margin for cooling04/02/2020FOCAL meetingCALICE info.: Tungsten plate not enough for heat dissipation Passive cooling with copper sheet (see next slide)
13. Pad-layer Design:Temperature simulation04/02/2020FOCAL meeting13Heat dissipation through ANSYS simulation, RT=20°C: ONE full pad-layer including W plate, Si-pad and PCB FEE board with embedded HGCROC chipsPCB enclosed between 2 successive W plates1mm thickness sheet of copper used for passive coolingTemperature variation for cooling from 0 °C up to 30°C Hot spot @ center of HGCROCwithout copper223.5 °C224.5°C47.3 °C49.65°C20°C33.28°Cedge of the copper plate (only 5mm) @ 20°CCan be achieved by forced air cooling or liquid cooling
14. Triggering options:Current option HGCROC Trigger Information (i.e. fast sum) connected to aggregator boardAllows local triggering:HGCROC only option 1Between 3 or 4 pad layers option 23 PCB needed:Pad layer boardInterface board Aggregator board1404/02/2020FOCAL meeting
15. Triggering options: Downgraded optionNo self triggering (ever!) External trigger ONLYTrigger information (i.e. fast sum) not connected to aggregator board Saving on FPGA cost and on PCB complexityNo need for vertical stacking one less PCB (i.e. Interface board)Lower power consumptionFlat architecture2 PCB needed:Pad layer boardAggregator boardCost – –1504/02/2020FOCAL meeting
16. Triggering options: upgraded optionVertical stackingSafe connecting between 5 aggregator boardsHigher complexity: PCB, FPGA and tuning3 PCB needed:Pad layer boardInterface boardAggregator boardCost ++1604/02/2020FOCAL meeting
17. KU035KU060Diff. HP I/O192240Single Ended HR I/O104104Cost (€)1.5k3.4k04/02/2020FOCAL meeting17